################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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温馨提示
简介:开发板Nexys4 DDR, 摄像头OV7670,是CMOS 图像传感器,最高分辨率640*480.将摄像头OV7670通过开发板的PMOD的IO接口相连,用VHDL/verilog进行编程,本实验用了两种语言分别编程通过,通过编程,摄像头采集的图像可以通过VGA传输实时的显示在显示屏上。代码适用于Xilinx系列开发板,altera系列需要修改部分代码。 整体思路:首先图像传感器OV7670采集图像通过PMOD口输入到内存RAM中,然后从RAM中实时提取像素并通过VGA实时显示在显示屏上。开发板时钟100M,经过分频,给OV7670驱动和VGA的时钟分别为50M和25M,内存RAM是通过XIlinx开发软件的vivado中的开源IP核调用,设置存储位宽和深度,用来存储一帧的图像数据,最后提取RAM中的这一阵像素到VGA上并显示。
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Nexys4 DDR + OV7670 摄像头实时监控系统 (207个子文件)
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
OV7670_top_verilog.bin 3.65MB
OV7670_top_verilog.bit 3.65MB
OV7670_top_verilog_routed.dcp 1.51MB
OV7670_top_verilog_placed.dcp 1.21MB
OV7670_top_verilog_opt.dcp 860KB
OV7670_top_verilog.dcp 707KB
compile.do 839B
compile.do 805B
compile.do 755B
compile.do 741B
simulate.do 339B
simulate.do 337B
simulate.do 337B
elaborate.do 211B
simulate.do 201B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
run.f 582B
run.f 562B
usage_statistics_webtalk.html 35KB
xsim.ini 26KB
vivado_5188.backup.jou 8KB
vivado_12720.backup.jou 4KB
vivado.jou 1KB
vivado.jou 964B
vivado.jou 959B
webtalk.jou 932B
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 2KB
rundef.js 1KB
runme.log 90KB
runme.log 36KB
vivado_5188.backup.log 13KB
vivado_12720.backup.log 8KB
vivado.log 3KB
ip_upgrade.log 1KB
webtalk.log 1001B
summary.log 991B
summary.log 991B
summary.log 991B
summary.log 991B
summary.log 991B
summary.log 991B
summary.log 991B
summary.log 991B
summary.log 991B
summary.log 991B
OV7670_NEXYS4_Verilog-master.lpr 343B
elab.opt 216B
vivado.pb 138KB
place_design.pb 20KB
route_design.pb 16KB
opt_design.pb 14KB
write_bitstream.pb 4KB
init_design.pb 3KB
OV7670_top_verilog_power_summary_routed.pb 722B
OV7670_top_verilog_utilization_synth.pb 242B
OV7670_top_verilog_utilization_placed.pb 242B
vivado.pb 149B
OV7670_top_verilog_timing_summary_routed.pb 106B
OV7670_top_verilog_methodology_drc_routed.pb 53B
OV7670_top_verilog_route_status.pb 44B
OV7670_top_verilog_drc_routed.pb 37B
OV7670_top_verilog_drc_opted.pb 37B
OV7670_top_verilog_bus_skew_routed.pb 30B
vlog.prj 168B
OV7670_top_verilog_io_placed.rpt 97KB
OV7670_top_verilog_methodology_drc_routed.rpt 87KB
OV7670_top_verilog_clock_utilization_routed.rpt 25KB
OV7670_top_verilog_timing_summary_routed.rpt 18KB
OV7670_top_verilog_utilization_placed.rpt 9KB
OV7670_top_verilog_power_routed.rpt 8KB
OV7670_top_verilog_utilization_synth.rpt 7KB
OV7670_top_verilog_control_sets_placed.rpt 5KB
OV7670_top_verilog_drc_routed.rpt 4KB
OV7670_top_verilog_drc_opted.rpt 4KB
OV7670_top_verilog_bus_skew_routed.rpt 980B
OV7670_top_verilog_route_status.rpt 588B
OV7670_top_verilog_power_routed.rpx 713KB
OV7670_top_verilog_timing_summary_routed.rpx 694KB
OV7670_top_verilog_methodology_drc_routed.rpx 161KB
OV7670_top_verilog_drc_routed.rpx 4KB
OV7670_top_verilog_drc_opted.rpx 4KB
OV7670_top_verilog_bus_skew_routed.rpx 1KB
.vivado.begin.rst 218B
.vivado.begin.rst 218B
.write_bitstream.begin.rst 179B
.place_design.begin.rst 179B
.route_design.begin.rst 179B
.init_design.begin.rst 179B
.opt_design.begin.rst 179B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
共 207 条
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资源评论
- you_ha1112022-12-21资源很实用,对我启发很大,有很好的参考价值,内容详细。
- weixin_447304702023-04-06这个资源总结的也太全面了吧,内容详实,对我帮助很大。
- ?#^%*?2023-02-07发现一个宝藏资源,赶紧冲冲冲!支持大佬~
- 2401_830997802024-03-01支持这个资源,内容详细,主要是能解决当下的问题,感谢大佬分享~
- 2201_757616172024-03-21资源内容详细全面,与描述一致,对我很有用,有一定的使用价值。
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