################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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【项目介绍】 基于Verilog的简易单周期CPU的实现+实验报告.zip 该资源内项目代码都是经过测试运行成功,功能ok的情况下才上传的,请放心下载使用! 本项目适合计算机相关专业(如计科、人工智能、通信工程、自动化、电子信息等)的在校学生、老师或者企业员工下载使用,也适合小白学习进阶, 或者实际项目借鉴参考! 当然也可作为毕设项目、课程设计、作业、项目初期立项演示等。如果基础还行,也可在此代码基础上进行修改,以实现其他功能。 简易单周期CPU的实现 **开发语言:** Verilog **开发平台:** Vivado 2018.3
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基于Verilog的简易单周期CPU的实现+实验报告.zip (412个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
mipstest.asm 1020B
xsim.ini.bak 22KB
elaborate.bat 921B
compile.bat 813B
simulate.bat 781B
runme.bat 219B
runme.bat 219B
runme.bat 219B
xsim_1.c 16KB
xsim_1.c 5KB
mipstest.coe 243B
mipstest.coe 243B
mipstest.coe 243B
mipstest.coe 243B
mipstest.coe 243B
mipstest.coe 243B
mipstest.coe 243B
mipstest.coe 243B
mipstest.coe 243B
mipstest.coe 243B
mipstest.coe 243B
xsim.dbg 152KB
xsim.dbg 6KB
top.dcp 136KB
data_mem.dcp 38KB
data_mem.dcp 36KB
data_mem.dcp 36KB
data_mem.dcp 36KB
data_mem.dcp 36KB
inst_mem.dcp 29KB
inst_mem.dcp 29KB
inst_mem.dcp 29KB
compile.do 730B
compile.do 730B
compile.do 696B
compile.do 696B
compile.do 646B
compile.do 646B
compile.do 632B
compile.do 632B
simulate.do 315B
simulate.do 315B
simulate.do 308B
simulate.do 308B
simulate.do 308B
simulate.do 308B
elaborate.do 202B
elaborate.do 202B
simulate.do 177B
simulate.do 177B
wave.do 30B
wave.do 30B
wave.do 30B
wave.do 30B
wave.do 30B
wave.do 30B
wave.do 30B
wave.do 30B
simulate.do 9B
simulate.do 9B
xsimk.exe 215KB
xsimk.exe 67KB
run.f 484B
run.f 484B
run.f 464B
run.f 464B
usage_statistics_ext_xsim.html 4KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 60B
.xsim_webtallk.info 59B
xsim.ini 22KB
xsim.ini 22KB
xsim.ini 22KB
xsimSettings.ini 1KB
xsimSettings.ini 1KB
webtalk.jou 905B
webtalk_12844.backup.jou 905B
webtalk_19060.backup.jou 905B
webtalk_8984.backup.jou 904B
webtalk_6280.backup.jou 904B
webtalk_5860.backup.jou 904B
vivado.jou 750B
vivado.jou 749B
vivado.jou 704B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 32KB
runme.log 32KB
runme.log 30KB
compile.log 3KB
xvlog.log 3KB
elaborate.log 2KB
webtalk.log 974B
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资源评论
- qwerty11122234332024-04-24兄弟你这结果都是错的
- weixin_554581752023-11-16感谢大佬分享的资源给了我灵感,果断支持!感谢分享~
- wangzheguilailu2023-12-03资源简直太好了,完美解决了当下遇到的难题,这样的资源很难不支持~
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