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datasheet DDR4 SDRAM
Rev.1.5
K4A8G165WC
Table Of Contents
8Gb C-die DDR4 SDRAM x16
1. Ordering Information............................................................................................................................................................................ 5
2. Key Features ....................................................................................................................................................................................... 5
3. Package pinout/Mechanical Dimension & Addressing ........................................................................................................................ 6
3.1 x16 Package Pinout (Top view): 96ball FBGA Package.................................................................................................................6
3.2 FBGA Package Dimension (x16)....................................................................................................................................................7
4. Input/Output Functional Description .................................................................................................................................................... 8
5. DDR4 SDRAM Addressing.................................................................................................................................................................. 10
6. Absolute Maximum Ratings................................................................................................................................................................. 11
6.1 Absolute Maximum DC Ratings......................................................................................................................................................11
6.2 DRAM Component Operating Temperature Range........................................................................................................................11
7. AC & DC Operating Conditions ........................................................................................................................................................... 11
8. AC & DC Input Measurement Levels................................................................................................................................................... 12
8.1 AC & DC Logic input levels for single-ended signals......................................................................................................................12
8.2 VREF Tolerances ...........................................................................................................................................................................12
8.3 AC & DC Logic Input Levels for Differential Signals ......................................................................................................................13
8.3.1. Differential signals definition ...................................................................................................................................................13
8.3.2. Differential swing requirement for clock (CK_t - CK_c)...........................................................................................................13
8.3.3. Single-ended requirements for differential signals..................................................................................................................14
8.3.4. Address, Command and Control Overshoot and Undershoot specifications..........................................................................15
8.3.5. Clock Overshoot and Undershoot Specifications....................................................................................................................16
8.3.6. Data, Strobe and Mask Overshoot and Undershoot Specifications........................................................................................17
8.4 Slew Rate Definitions......................................................................................................................................................................18
8.4.1. Slew Rate Definitions for Differential Input Signals (CK) ........................................................................................................18
8.4.2. Slew Rate Definition for Single-ended Input Signals ( CMD/ADD ) ........................................................................................19
8.5 Differential Input Cross Point Voltage.............................................................................................................................................20
8.6 CMOS rail to rail Input Levels .........................................................................................................................................................21
8.6.1. CMOS rail to rail Input Levels for RESET_n ...........................................................................................................................21
8.7 AC and DC Logic Input Levels for DQS Signals.............................................................................................................................22
8.7.1. Differential signal definition .....................................................................................................................................................22
8.7.2. Differential swing requirements for DQS (DQS_t - DQS_c)....................................................................................................22
8.7.3. Peak voltage calculation method ............................................................................................................................................23
8.7.4. Differential Input Cross Point Voltage .....................................................................................................................................24
8.7.5. Differential Input Slew Rate Definition ....................................................................................................................................25
9. AC and DC output Measurement levels .............................................................................................................................................. 26
9.1 Output Driver DC Electrical Characteristics....................................................................................................................................26
9.1.1. Alert_n output Drive Characteristic .........................................................................................................................................28
9.1.2. Output Driver Characteristic of Connectivity Test ( CT ) Mode...............................................................................................28
9.2 Single-ended AC & DC Output Levels............................................................................................................................................29
9.3 Differential AC & DC Output Levels................................................................................................................................................29
9.4 Single-ended Output Slew Rate .....................................................................................................................................................30
9.5 Differential Output Slew Rate .........................................................................................................................................................31
9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode .................................................................................................32
9.7 Test Load for Connectivity Test Mode Timing ................................................................................................................................32
10. Speed Bin .......................................................................................................................................................................................... 33
10.1 Speed Bin Table Note...................................................................................................................................................................38
11. IDD and IDDQ Specification Parameters and Test conditions .......................................................................................................... 39
11.1 IDD, IPP and IDDQ Measurement Conditions..............................................................................................................................39
12. 8Gb DDR4 SDRAM C-die IDD Specification Table........................................................................................................................... 54
13. Input/Output Capacitance.................................................................................................................................................................. 56
14. Electrical Characteristics & AC Timing .............................................................................................................................................. 58
14.1 Reference Load for AC Timing and Output Slew Rate .................................................................................................................58
14.2 tREFI.............................................................................................................................................................................................58
14.3 Clock Specification .......................................................................................................................................................................59
14.3.1. Definition for tCK(abs)...........................................................................................................................................................59
14.3.2. Definition for tCK(avg)...........................................................................................................................................................59
14.3.3. Definition for tCH(avg) and tCL(avg)....................................................................................................................................59
14.3.4. Definition for tERR(nper).......................................................................................................................................................59
14.4 Timing Parameters by Speed Grade ............................................................................................................................................60
14.5 Rounding Algorithms ...................................................................................................................................................................66
14.6 The DQ input receiver compliance mask for voltage and timing ..................................................................................................67
14.7 DDR4 Function Matrix ..................................................................................................................................................................71
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