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JEDEC Standard No. 21C
Page 4.20.23-1
Release 22 Revision 0.92
4.20.23 - 240-Pin, 72 bit-wide, PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-
14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification
DDR3 SDRAM Registered DIMM Design Specification
Revision 0.92
December 2012
Revision 0.92 Release 22
JEDEC Standard No. 21C
Page 4.20.23-2
Contents
1. Product Description.................................................................................................................... ........... 4
Product Family Attributes............................................................................................................ ........... 4
2. Environmental Requirements................................................................................................................ 5
3. Pinout and Description............................................................................................................... ........... 6
Pin Description............................................................................................................................ ...........6
Input/Output Functional Description.......................................................................................................7
DDR3 240-pin DIMM Pinout...................................................................................................................9
Pinout Comparison...............................................................................................................................10
4. Component Details.................................................................................................................... ...........11
Pin Assignments for 512Mb to 8Gb; DDR3 SDRAM............................................................................12
PCB Pad Array Options for SDRAM Placements...................................................................... .......... 17
Pin Assignments for Registering Clock Driver............................................................................ .........23
Critical Registering Clock Driver Specifications (Reference Only).............................................. .........25
Pin Assignments for Serial Presence Detect.............................................................................. .........27
5. DDR3 Registered DIMM Wiring Details...............................................................................................28
Signal Groups............................................................................................................................. .........28
General Net Structure Routing Guidelines...........................................................................................28
Test Point.................................................................................................................................... .........30
Explanation of Net Structure Diagrams................................................................................................ 31
6. Timing Budget.......................................................................................................................................32
Example of DDR3 Timing Budget............................................................................................... .........33
7. On DIMM Thermal Sensor........................................................................................................... ......... 34
8. Register Clock Driver (RCD) Feedback Topology..................................................................... ........35
9. Serial Presence Detect Definition............................................................................................... ........36
10. DDR3 DIMM Label Format..................................................................................................................39
11. DIMM Mechanical Specifications............................................................................................... ....... 41
12. Design File Naming Convention........................................................................................................ 42
Annex A - Raw Card A............................................................................................................................. A1
Annex B - Raw Card B............................................................................................................................. B1
Annex C - Raw Card C..............................................................................................................................C1
JEDEC Standard No. 21C
Page 4.20.23-3
Release 22 Revision 0.92
Annex D - Raw Card D..............................................................................................................................D1
Annex E - Raw Card E........................................................................................................................ ......E1
Annex G - Raw Card G............................................................................................................................ .G1
Annex H - Raw Card H..............................................................................................................................H1
Annex J - Raw Card J .............................................................................................................................. J1
Annex K - Raw Card K..............................................................................................................................K1
Annex L - Raw Card L............................................................................................................................. . L1
Annex M - Raw Card M............................................................................................................................ M1
Annex N - Raw Card N..............................................................................................................................N1
Annex V - Raw Card V............................................................................................................................ .. V1
Annex W - Raw Card W.......................................................................................................................... . W1
Annex Y - Raw Card Y............................................................................................................................ .. Y1
Annex AB - Raw Card AB...................................................................................................................... AB1
Annex AD - Raw Card AD...................................................................................................................... AD1
Revision 0.92 Release 22
JEDEC Standard No. 21C
Page 4.20.23-4
1 Product Description
This specification defines the electrical and mechanical requirements for 240-pin, 72 bit-wide, Registered
Double Data Rate Synchronous DRAM Dual In-Line Memory Modules (DDR3 SDRAM DIMMs). These
SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and
workstations.
PC3 refers to DIMMs designed to operate at 1.5V nominal. PC3L refers to DIMMs with components that can
support 1.35V nominal. PC3U refers to DIMMs with components that can support 1.25V nominal.
PC3(L,U)-6400, PC3(L,U)-8500, PC3(L,U)-10600, PC3(L,U)-12800, PC3-14900, PC3-17000 refers to the
JEDEC standard DIMM naming convention in which PC3(L,U)-6400, PC3(L,U)-8500, PC3(L,U)-10600,
PC(L,U)-12800, PC3-14900 and PC3-17000 indicates a DIMM running at 400, 533, 667, 800, 931 and 1063
MHz clock speed and offering 6400, 8500, 10600, 12800, 14900 and 17000 MB/s bandwidth.
Reference design examples are included which provide an initial basis for Registered DIMM designs.
Modifications to these reference designs may be required to meet all system timing, signal integrity, and
thermal requirements for PC3(L,U)-6400, PC3(L,U)-8500, PC3(L,U)-10600, PC3(L,U)-12800, PC3-14900
and PC3-17000 support. All registered DIMM implementations must use simulations and lab verification to
ensure proper timing requirements and signal integrity in the design.
DDR3 and DDR3L and DDR3U (PC3 and PC3L and PC3U) have different requirements. Many of the initial
designs were only simulated and tested based on 1.5V requirements. Speed grades and voltages for each
reference design are defined in each appendix. DDR3 refers to 1.5V operation only. For the design to be
1.35V capable the appendix must specifically include DDR3L. For the design to be 1.25V capable the
appendix must specifically include DDR3U.
Product Family Attributes
DIMM organization x72 ECC
DIMM dimensions : height (nom.) x width (nom.) x thickness (max.)
/ MO-number, Variation
30.0 mm x 133.35 mm x 4.00 mm / MO-269, Variation AB
30.0 mm x 133.35 mm x 6.75 mm / MO-269, Variation BB
30.0 mm x 133.35 mm x 7.55 mm / MO-269, Variation CB
18.75 mm x 133.35 mm x 4.00 mm / MO-269, Variation DB
18.75 mm x 133.35 mm x 6.75 mm / MO-269, Variation EB
18.75 mm x 133.35 mm x 7.55 mm / MO-269, Variation FB
Pin count 240
SDRAMs supported
512 Mb, 1 Gb, 2 Gb, 4 Gb, 8Gb
Capacity 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB
Serial PD Consistent with JC 45
Voltage options
1.25 volts or 1.35 volts or 1.5 volts (V
DD
), 3.3 volt (V
DDSPD
)
Interface
1.25 volt or 1.35 volt or 1.5 volt signal switching based on ref-
erence voltage at VDD/2. See DRAM specification for more
detail.
JEDEC Standard No. 21C
Page 4.20.23-5
Release 22 Revision 0.92
2 Environmental Requirements
DDR3 SDRAM Registered DIMMs are intended for use in standard office environments that have limited
capacity for heating and air conditioning.
Environmental Parameters
Symbol Parameter Rating Units Notes
T
OPR
Operating temperature See Note 3
H
OPR
Operating humidity (relative) 10 to 90 % 1
T
STG
Storage temperature -50 to +100 °C 1
H
STG
Storage humidity (without condensation) 5 to 95 % 1
P
BAR
Barometric pressure (operating & storage) 105 to 69 K Pascal 1, 2
Note 1 Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device func-
tional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Note 2 Up to 9850 ft.
Note 3 The designer must meet the case temperature specifications for individual module components.
剩余41页未读,继续阅读
资源评论
- typ_adam2016-09-28这个对DDR3的流程讲得比较细,对我有很大帮助
- soo39311232014-03-14不错,但是不是我想要的
- freezing6162015-01-15不错,此文只在本站有!
- baidu_166115932014-06-17太好了,内容充实,正是我想要的。
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