DDR3SDRAMSpecification_ddr3芯片引脚定义资源-CSDN文库

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This document defines the DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This specification was created based on the DDR2 specification (JESD79-2) and some aspects of the DDR specification (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballot(s). The accumulation of these ballots were then incorporated to prepare this JESD79-3 specification, replacing whole sections and incorporating the changes into Functional Description and Operation. 其實加入JEDEC會員即可下載，不想麻煩的人可以給我一點積分 ### DDR3 SDRAM 规范概述 #### 一、引言 DDR3 SDRAM（Double Data Rate Third Generation Synchronous Dynamic Random Access Memory）是继DDR2之后的一种同步动态随机存取内存技术标准，由JEDEC（Joint Electron Device Engineering Council）制定发布。本规范文档《DDR3 SDRAM Specification》（JESD79-3E）详细定义了DDR3 SDRAM的技术规格，包括特征、功能、交流和直流特性、封装类型以及球/信号分配等内容。 #### 二、规范目的本规范的主要目的是定义符合JEDEC标准的512Mb至8Gb容量范围内的x4、x8和x16 DDR3 SDRAM器件的最低要求。这些要求覆盖了DDR3 SDRAM的各种操作模式和技术细节，确保不同制造商之间的产品具有互换性和一致性。 #### 三、规范制定背景本规范基于DDR2规范（JESD79-2）和部分DDR规范（JESD79）制定而成，并通过委员会投票的方式进行了修订和完善。文档中的每个更改都经过了仔细考虑和批准，最终形成了这份JESD79-3规范。 #### 四、主要内容概述 - **特征与功能**：这部分详细介绍了DDR3 SDRAM的主要特点，如更高的数据传输速率、更低的功耗等。 - **交流和直流特性**：这部分描述了DDR3 SDRAM在工作时的电气性能指标，包括电压、电流等参数。 - **封装类型**：定义了DDR3 SDRAM的物理封装形式，包括BGA（Ball Grid Array）和其他类型的封装。 - **球/信号分配**：这部分说明了DDR3 SDRAM芯片上各个引脚的功能分配。 #### 五、技术细节解析 ##### 1. 数据传输速率 DDR3 SDRAM的数据传输速率达到2133MT/s（兆次传输/秒），相比于DDR2有显著提升。这是通过提高内存总线的速度和采用更高效的预取架构实现的。 ##### 2. 功耗降低 DDR3 SDRAM采用了更低的工作电压（1.5V），相比DDR2（1.8V）进一步降低了功耗。此外，DDR3还引入了电源管理功能，如自刷新（Self-Refresh）和扩展温度范围支持，从而提高了能效。 ##### 3. 内存带宽 DDR3 SDRAM提供了更高的内存带宽，这对于高性能计算应用至关重要。通过优化内部结构和提高预取宽度，DDR3能够提供比DDR2更高的数据吞吐量。 ##### 4. 封装类型 DDR3 SDRAM采用了不同的封装技术，包括BGA（Ball Grid Array）、FB-DIMM（Fully Buffered DIMM）等。这些封装技术不仅有助于减少信号干扰，还提高了内存模块的密度。 ##### 5. 球/信号分配为了确保信号完整性和稳定性，DDR3 SDRAM对引脚布局进行了优化。例如，地址线、命令/控制线和数据线被精心设计以减少相互间的干扰。 #### 六、规范的法律声明与使用指南 - **版权声明**：该文档版权归JEDEC所有，允许免费下载，但禁止未经许可的商业销售或分发。 - **规范遵循**：任何声称符合此规范的产品必须满足规范中所述的所有要求。 - **联系方式**：针对文档内容的问题和建议可以通过指定方式联系JEDEC。 #### 七、结论《DDR3 SDRAM Specification》（JESD79-3E）是一份详尽的技术规范文档，为DDR3 SDRAM的设计、制造和使用提供了全面指导。通过对本规范的学习和理解，可以更好地掌握DDR3 SDRAM的技术细节及其应用场景，对于硬件工程师、系统设计师以及相关领域的研究人员来说具有重要的参考价值。

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JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

JESD79-3E

July 2010

JEDEC

STANDARD

DDR3 SDRAM Specification

(Revision of JESD79-3D, August 2009)

NOTICE

JEDEC standards and publications contain material that has been prepared, reviewed, and

approved through the JEDEC Board of Directors level and subsequently reviewed and approved

by the JEDEC legal counsel.

JEDEC standards and publications are designed to serve the public interest through eliminating

misunderstandings between manufacturers and purchasers, facilitating interchangeability and

improvement of products, and assisting the purchaser in selecting and obtaining with minimum

delay the proper product for use by those other than JEDEC members, whether the standard is to

be used either domestically or internationally.

JEDEC standards and publications are adopted without regard to whether or not their adoption

may involve patents or articles, materials, or processes. By such action JEDEC does not assume

any liability to any patent owner, nor does it assume any obligation whatever to parties adopting

the JEDEC standards or publications.

The information included in JEDEC standards and publications represents a sound approach to

product specification and application, principally from the solid state device manufacturer

viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or

publication may be further processed and ultimately become an ANSI standard.

No claims to be in conformance with this standard may be made unless all requirements stated in

the standard are met.

Inquiries, comments, and suggestions relative to the content of this JEDEC standard or

publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or

www.jedec.org

Published by

©JEDEC Solid State Technology Association 2010

3103 North 10th Street, Suite 240 South

Arlington, VA 22201

This document may be downloaded free of charge; however JEDEC retains the copyright on this

material. By downloading this file the individual agrees not to charge for or resell the resulting

material.

PRICE: Please refer to the current

Catalog of JEDEC Engineering Standards and Publications online at

http://www.jedec.org/Catalog/catalog.cfm

Printed in the U.S.A.

JEDEC Standard No. 79-3E

Contents

1 Scope..........................................................................................................................................1

2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3

2.1 DDR3 SDRAM x4 Ballout using MO-207........................................................................3

2.2 DDR3 SDRAM x8 Ballout using MO-207........................................................................4

2.3 DDR3 SDRAM x16 Ballout using MO-207......................................................................5

2.4 Stacked / dual-die DDR3 SDRAM x4 Ballout using MO-207..........................................6

2.5 Stacked / dual-die DDR3 SDRAM x8 Ballout using MO-207..........................................7

2.6 Stacked / dual-die DDR3 SDRAM x16 Ballout using MO-207........................................8

2.7 Quad-stacked / Quad-die DDR3 SDRAM x4 Ballout using MO-207...............................9

2.8 Quad-stacked / Quad-die DDR3 SDRAM x8 Ballout using MO-207.............................10

2.9 Quad-stacked / Quad-die DDR3 SDRAM x16 Ballout using MO-207...........................11

2.10 Pinout Description..........................................................................................................13

2.11 DDR3 SDRAM Addressing...........................................................................................15

2.11.1 512Mb ....................................................................................................................15

2.11.2 1Gb..........................................................................................................................15

2.11.3 2Gb .........................................................................................................................15

2.11.4 4Gb .........................................................................................................................15

2.11.5 8Gb .........................................................................................................................16

3 Functional Description.............................................................................................................17

3.1 Simplified State Diagram.................................................................................................17

3.2 Basic Functionality ..........................................................................................................18

3.3 RESET and Initialization Procedure ................................................................................19

3.3.1 Power-up Initialization Sequence .............................................................................19

3.3.2 Reset Initialization with Stable Power......................................................................21

3.4 Register Definition...........................................................................................................22

3.4.1 Programming the Mode Registers ............................................................................22

3.4.2 Mode Register MR0..................................................................................................23

3.4.3 Mode Register MR1..................................................................................................27

3.4.4 Mode Register MR2..................................................................................................30

3.4.5 Mode Register MR3..................................................................................................32

4 DDR3 SDRAM Command Description and Operation...........................................................33

4.1 Command Truth Table .....................................................................................................33

4.2 CKE Truth Table..............................................................................................................35

4.3 No OPeration (NOP) Command ......................................................................................36

4.4 Deselect Command ..........................................................................................................36

4.5 DLL-off Mode..................................................................................................................37

4.6 DLL on/off switching procedure......................................................................................38

4.6.1 DLL “on” to DLL “off” Procedure...........................................................................38

4.6.2 DLL “off” to DLL “on” Procedure...........................................................................39

4.7 Input clock frequency change ..........................................................................................40

4.8 Write Leveling .................................................................................................................42

4.8.1 DRAM setting for write leveling & DRAM termination function in that mode ......43

4.8.2 Procedure Description...............................................................................................43

4.8.3 Write Leveling Mode Exit ........................................................................................45

剩余225页未读，继续阅读

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2012-05-21

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