Revision 1.10 Release 25A
JEDEC Standard No. 21C
Page 4.20.28-2
Table of Contents
1 Product Description ................................................................................................. 5
2 Environmental Requirements .................................................................................. 6
3 Connector Pinout and Signal Description................................................................ 7
4 Power Details ........................................................................................................ 12
4.1 DIMM Voltage Requirements..................................................................................................12
4.2 VDDSPD .................................................................................................................. 12
4.3 Recommended Power Sequence ............................................................................. 12
4.4 Feed Through Voltage (VFT) .................................................................................... 14
4.5 12 V Power................................................................................................................ 14
5 Component Details................................................................................................ 15
5.1 Component Types and Placement............................................................................ 18
5.2 Decoupling Guidelines .............................................................................................. 18
6 DIMM Design Details............................................................................................. 19
6.1 Signal Groups ........................................................................................................... 19
6.2 General Net Structure Routing Rules........................................................................ 19
6.2.1 Clock, Control, and Address/Command Groups ........................................................... 20
6.2.2 PreRegister ADD/CMD and CTRL ................................................................................21
6.2.3 PreRegister CK .............................................................................................................21
6.2.4 PostRegister ADD/CMD ................................................................................................22
6.2.5 PostRegister CTRL Group ............................................................................................ 22
6.2.6 DQ Group ......................................................................................................................23
6.3 Plane Referencing..................................................................................................... 24
6.4 Address Mirroring...................................................................................................... 24
6.5 DQ Mapping to Support CRC.................................................................................... 25
6.6 DIMM Routing Space Constraints............................................................................. 28
6.7 DIMM Physical Requirements................................................................................... 29
6.7.1 Via Size .........................................................................................................................29
6.7.2 Component Pad Sizes and Geometry...........................................................................29
6.7.3 SDRAM Package Size ..................................................................................................29
6.7.4 Clock Termination .........................................................................................................29
6.7.5 DQ Resistor...................................................................................................................29
6.8 RDIMM Configuration................................................................................................ 30
6.8.1 Control Wiring................................................................................................................30
6.8.2 AVDD Filter Circuit, Placement and Wiring ................................................................... 31
6.8.3 ZQ Calibration Wiring ....................................................................................................32
6.8.4 ALERT_n Circuit Wiring ................................................................................................32
6.8.5 TEN Pin Wiring ..............................................................................................................32
6.9 SPD-TSE Selection, Wiring and Placement.............................................................. 33
7 Serial Presence Detect (Pending Separate Ballot) ............................................... 34
7.1 Serial Presence Detect Definition ............................................................................. 34
8 Product Label ........................................................................................................ 37
9 JEDEC Process..................................................................................................... 41
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qq_181934912024-03-20非常不粗，正在设计一款内存条，可以参考规范。
