Revision 1.10 Release 25A
JEDEC Standard No. 21C
Page 4.20.25-2
Table of Contents
1 Product Description .......................................................................................................... 5
2 Environmental Requirements........................................................................................... 6
3 Connector Pinout and Signal Description....................................................................... 7
3.1 DDR4 SO-DIMM Connector Pin Assignments .....................................................................................10
4 Power Details ................................................................................................................... 12
4.1 DIMM Voltage Requirements ................................................................................................................12
4.2 Rules for Power-Up Sequence..............................................................................................................13
4.3 Feed Through Voltage (VFT).................................................................................................................13
5 Component Details.......................................................................................................... 15
5.1 Component Types and Placement .......................................................................................................18
5.2 Decoupling Guidelines..........................................................................................................................18
6 DIMM Design Details ....................................................................................................... 19
6.1 Signal Groups ........................................................................................................................................19
6.2 Explanation of Net Structure Diagrams...............................................................................................19
6.3 General Net Structure Routing Rules ..................................................................................................20
6.3.1 Clock, Control, and Address/Command Groups ........................................................... 20
6.3.2 Lead-in vs. Loaded Sections ......................................................................................... 21
6.3.3 Length/Delay Matching to SDRAM Devices..................................................................21
6.3.4 Velocity Compensation.................................................................................................. 22
6.3.5 Load/Delay Compensation ............................................................................................22
6.3.6 Data and Strobe Group .................................................................................................22
6.3.7 ALERT_n Wiring............................................................................................................23
6.3.8 Via Compensation .........................................................................................................23
6.3.9 Plane Referencing.........................................................................................................25
6.4 Address Mirroring..................................................................................................................................25
6.5 DIMM Routing Space Constraints ........................................................................................................26
6.6 DIMM Physical Requirements...............................................................................................................27
6.6.1 Via Size .........................................................................................................................27
6.6.2 Component Pad Sizes and Geometry...........................................................................27
6.6.3 DRAM Package Size .....................................................................................................27
6.6.4 Clock Termination .........................................................................................................27
6.6.5 ZQ Calibration Wiring ....................................................................................................27
6.6.6 DQ Stub Resistor ..........................................................................................................28
6.6.7 TEN Wiring ....................................................................................................................28
6.7 Reference Stackups...............................................................................................................................28
6.8 Impedance Targets ................................................................................................................................30
6.9 SPD Wiring and Placement ...................................................................................................................31
6.10 DQ Mapping to Support CRC................................................................................................................32
7 Serial Presence Detect Component Specification........................................................ 35
7.1 Serial Presence Detect Definition.........................................................................................................35
8 Product Label................................................................................................................... 37
8.1 DDR4 DIMM Label Format for DRAM-only module types...................................................................37
8.2 DDR4 DIMM Label Format for Hybrid module types...........................................................................41
9 JEDEC Process................................................................................................................ 44
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