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DDR4 SDRAM

EDY4016A - 256Mb x 16

Features

•V

= V

DDQ

= 1.2V ±60mV

•V

= 2.5V, –125mV/+250mV

• On-die, internal, adjustable V

REFDQ

generation

• 1.2V pseudo open-drain I/O

•T

of 0°C to 95°C

– 64ms, 8192-cycle refresh at 0°C to 85°C

– 32ms at 85°C to 95°C

• 8 internal banks: 2 groups of 4 banks each

•8n-bit prefetch architecture

• Programmable data strobe preambles

• Data strobe preamble training

• Command/Address latency (CAL)

• Multipurpose register READ and WRITE capability

• Write and read leveling

• Self refresh mode

• Low-power auto self refresh (LPASR)

• Temperature controlled refresh (TCR)

• Fine granularity refresh

• Self refresh abort

• Maximum power saving

• Output driver calibration

• Nominal, park, and dynamic on-die termination

(ODT)

• Data bus inversion (DBI) for data bus

• Command/Address (CA) parity

• Databus write cyclic redundancy check (CRC)

• Per-DRAM addressability

• Connectivity test

• JEDEC JESD-79-4 compliant

Options

Marking

• Revision A

• FBGA package size

– 96-ball (7.5mm x 13.5mm) BG

• Timing – cycle time

– 0.625ns @ CL = 24 (DDR4-3200) -JD

– 0.750ns @ CL = 19 (DDR4-2666) -GX

– 0.833ns @ CL = 16 (DDR4-2400) -DR

• Packaging

– Lead-free (RoHS-compliant) and hal-

ogen-free

- F

Notes:

1. Not all options listed can be combined to

define an offered product. Use the part

catalog search on http://www.micron.com

for available offerings.

2. Restricted and limited availability.

Table 1: Key Timing Parameters

Speed Grade Data Rate (MT/s) Target

RCD-

RP-CL

RCD (ns)

RP (ns) CL (ns)

-JD

3200 24-24-24 15.0 15.0 15.0

-GX

2666 19-19-19 14.25 14.25 14.25

-DR

2400 16-16-16 13.32 13.32 13.32

Notes:

1. Backward compatible to 2666 CL = 20, 2400 CL = 18), 2133 CL = 16, 1866 CL = 14, 1600 CL = 12.

2. Backward compatible to 2400 CL = 17, 2133 CL = 15, 1866 CL = 13, 1600 CL = 11.

3. Backward compatible to 2133 CL = 15, 1866 CL = 13, 1600 CL = 11.

Table 2: Addressing

Parameter 256 Meg x 16

Number of bank groups 2

Bank group address BG0

4Gb: x16 DDR4 SDRAM

Features

PDF: 09005aef85f537bf

4gb_ddr4_dram_2e0d.pdf - Rev. E 7/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Contents

General Notes and Description ....................................................................................................................... 18

Description ................................................................................................................................................ 18

Industrial Temperature ............................................................................................................................... 18

General Notes ............................................................................................................................................ 18

Definitions of the Device-Pin Signal Level ................................................................................................... 19

Definitions of the Bus Signal Level ............................................................................................................... 19

Ball Assignments ............................................................................................................................................ 20

Ball Descriptions ............................................................................................................................................ 21

Package Dimensions ....................................................................................................................................... 24

State Diagram ................................................................................................................................................ 25

Functional Description ................................................................................................................................... 27

RESET and Initialization Procedure ................................................................................................................. 28

Power-Up and Initialization Sequence ......................................................................................................... 28

RESET Initialization with Stable Power Sequence ......................................................................................... 31

Uncontrolled Power-Down Sequence .......................................................................................................... 32

Programming Mode Registers ......................................................................................................................... 33

Mode Register 0 .............................................................................................................................................. 36

Burst Length, Type, and Order ..................................................................................................................... 38

CAS Latency ............................................................................................................................................... 39

Test Mode .................................................................................................................................................. 39

Write Recovery(WR)/READ-to-PRECHARGE ............................................................................................... 39

DLL RESET ................................................................................................................................................. 39

Mode Register 1 .............................................................................................................................................. 40

DLL Enable/DLL Disable ............................................................................................................................ 41

Output Driver Impedance Control ............................................................................................................... 42

ODT R

TT(NOM)

Values .................................................................................................................................. 42

Additive Latency ......................................................................................................................................... 42

DQ RX EQ .................................................................................................................................................. 42

Write Leveling ............................................................................................................................................ 43

Output Disable ........................................................................................................................................... 43

Termination Data Strobe ............................................................................................................................. 43

Mode Register 2 .............................................................................................................................................. 44

CAS WRITE Latency .................................................................................................................................... 46

Low-Power Auto Self Refresh ....................................................................................................................... 46

Dynamic ODT ............................................................................................................................................ 46

Write Cyclic Redundancy Check Data Bus .................................................................................................... 46

Mode Register 3 .............................................................................................................................................. 47

Multipurpose Register ................................................................................................................................ 48

WRITE Command Latency When CRC/DM is Enabled ................................................................................. 49

Fine Granularity Refresh Mode .................................................................................................................... 49

Temperature Sensor Status ......................................................................................................................... 49

Per-DRAM Addressability ........................................................................................................................... 49

Gear-Down Mode ....................................................................................................................................... 49

Mode Register 4 .............................................................................................................................................. 50

Hard Post Package Repair Mode .................................................................................................................. 51

Soft Post Package Repair Mode .................................................................................................................... 52

WRITE Preamble ........................................................................................................................................ 52

READ Preamble .......................................................................................................................................... 52

READ Preamble Training ............................................................................................................................ 52

Temperature-Controlled Refresh ................................................................................................................. 52

4Gb: x16 DDR4 SDRAM

Features

PDF: 09005aef85f537bf

4gb_ddr4_dram_2e0d.pdf - Rev. E 7/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Command Address Latency ........................................................................................................................ 52

Internal V

REF

Monitor ................................................................................................................................. 52

Maximum Power Savings Mode ................................................................................................................... 53

Mode Register 5 .............................................................................................................................................. 54

Data Bus Inversion ..................................................................................................................................... 55

Data Mask .................................................................................................................................................. 56

CA Parity Persistent Error Mode .................................................................................................................. 56

ODT Input Buffer for Power-Down .............................................................................................................. 56

CA Parity Error Status ................................................................................................................................. 56

CRC Error Status ......................................................................................................................................... 56

CA Parity Latency Mode .............................................................................................................................. 56

Mode Register 6 .............................................................................................................................................. 57

CCD_L Programming ................................................................................................................................. 58

REFDQ

Calibration Enable .......................................................................................................................... 58

REFDQ

Calibration Range ........................................................................................................................... 58

REFDQ

Calibration Value ............................................................................................................................ 59

DQ RX EQ .................................................................................................................................................. 59

Truth Tables ................................................................................................................................................... 60

NOP Command .............................................................................................................................................. 63

DESELECT Command .................................................................................................................................... 63

DLL-Off Mode ................................................................................................................................................ 63

DLL-On/Off Switching Procedures .................................................................................................................. 65

DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 65

DLL-Off to DLL-On Procedure .................................................................................................................... 66

Input Clock Frequency Change ....................................................................................................................... 67

Write Leveling ................................................................................................................................................ 68

DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 70

Procedure Description ................................................................................................................................ 71

Write Leveling Mode Exit ............................................................................................................................ 72

Command Address Latency ............................................................................................................................ 73

Low-Power Auto Self Refresh Mode ................................................................................................................. 78

Manual Self Refresh Mode .......................................................................................................................... 78

Multipurpose Register .................................................................................................................................... 80

MPR Reads ................................................................................................................................................. 81

MPR Readout Format ................................................................................................................................. 83

MPR Readout Serial Format ........................................................................................................................ 83

MPR Readout Parallel Format ..................................................................................................................... 84

MPR Readout Staggered Format .................................................................................................................. 85

MPR READ Waveforms ............................................................................................................................... 86

MPR Writes ................................................................................................................................................ 88

MPR WRITE Waveforms .............................................................................................................................. 89

MPR REFRESH Waveforms ......................................................................................................................... 90

Gear-Down Mode ........................................................................................................................................... 93

Maximum Power-Saving Mode ........................................................................................................................ 96

Maximum Power-Saving Mode Entry ........................................................................................................... 96

Maximum Power-Saving Mode Entry in PDA ............................................................................................... 97

CKE Transition During Maximum Power-Saving Mode ................................................................................. 97

Maximum Power-Saving Mode Exit ............................................................................................................. 97

Command/Address Parity ............................................................................................................................... 99

Per-DRAM Addressability .............................................................................................................................. 107

REFDQ

Calibration ........................................................................................................................................ 110

REFDQ

Range and Levels ........................................................................................................................... 111

4Gb: x16 DDR4 SDRAM

Features

PDF: 09005aef85f537bf

4gb_ddr4_dram_2e0d.pdf - Rev. E 7/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

REFDQ

Step Size ........................................................................................................................................ 111

REFDQ

Increment and Decrement Timing .................................................................................................. 112

REFDQ

Target Settings ............................................................................................................................... 116

Connectivity Test Mode ................................................................................................................................. 118

Pin Mapping ............................................................................................................................................. 118

Minimum Terms Definition for Logic Equations ......................................................................................... 119

Logic Equations for a ×4 Device .................................................................................................................. 119

Logic Equations for a ×8 Device .................................................................................................................. 120

Logic Equations for a ×16 Device ................................................................................................................ 120

CT Input Timing Requirements .................................................................................................................. 120

Post Package Repair ....................................................................................................................................... 122

Post Package Repair ................................................................................................................................... 122

Hard Post Package Repair .......................................................................................................................... 123

hPPR Row Repair - Entry ........................................................................................................................ 123

hPPR Row Repair – WRA Initiated (REF Commands Allowed) .................................................................. 123

hPPR Row Repair – WR Initiated (REF Commands NOT Allowed) ............................................................. 125

sPPR Row Repair ....................................................................................................................................... 127

hPPR/sPPR Support Identifier .................................................................................................................... 130

Excessive Row Activation ............................................................................................................................... 131

ACTIVATE Command .................................................................................................................................... 131

PRECHARGE Command ................................................................................................................................ 132

REFRESH Command ..................................................................................................................................... 133

Temperature-Controlled Refresh Mode .......................................................................................................... 135

TCR Mode – Normal Temperature Range .................................................................................................... 135

TCR Mode – Extended Temperature Range ................................................................................................. 135

Fine Granularity Refresh Mode ....................................................................................................................... 137

Mode Register and Command Truth Table .................................................................................................. 137

REFI and

RFC Parameters ........................................................................................................................ 137

Changing Refresh Rate ............................................................................................................................... 140

Usage with TCR Mode ................................................................................................................................ 140

Self Refresh Entry and Exit ......................................................................................................................... 140

SELF REFRESH Operation .............................................................................................................................. 142

Self Refresh Abort ...................................................................................................................................... 144

Self Refresh Exit with NOP Command ......................................................................................................... 145

Power-Down Mode ........................................................................................................................................ 147

Power-Down Clarifications – Case 1 ........................................................................................................... 152

Power-Down Entry, Exit Timing with CAL ................................................................................................... 153

ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 155

CRC Write Data Feature ................................................................................................................................. 157

CRC Write Data ......................................................................................................................................... 157

WRITE CRC DATA Operation ...................................................................................................................... 157

DBI_n and CRC Both Enabled .................................................................................................................... 158

DM_n and CRC Both Enabled .................................................................................................................... 158

DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 158

CRC and Write Preamble Restrictions ......................................................................................................... 158

CRC Simultaneous Operation Restrictions .................................................................................................. 158

CRC Polynomial ........................................................................................................................................ 158

CRC Combinatorial Logic Equations .......................................................................................................... 159

Burst Ordering for BL8 ............................................................................................................................... 160

CRC Data Bit Mapping ............................................................................................................................... 160

CRC Enabled With BC4 .............................................................................................................................. 161

CRC with BC4 Data Bit Mapping ................................................................................................................ 161

4Gb: x16 DDR4 SDRAM

Features

PDF: 09005aef85f537bf

4gb_ddr4_dram_2e0d.pdf - Rev. E 7/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.