module LED(data,a,b,c,d,e,f,g);
input [3:0]data;
output a,b,c,d,e,f,g;
reg a,b,c,d,e,f,g;
always@ (data)
begin case(data)4'd0:{a,b,c,d,e,f,g}=7'b0000001;
4'd1:{a,b,c,d,e,f,g}=7'b1001111;
4'd2:{a,b,c,d,e,f,g}=7'b0010010;
4'd3:{a,b,c,d,e,f,g}=7'b0000110;
4'd4:{a,b,c,d,e,f,g}=7'b1001100;
4'd5:{a,b,c,d,e,f,g}=7'b0100100;
4'd6:{a,b,c,d,e,f,g}=7'b0100000;
4'd7:{a,b,c,d,e,f,g}=7'b0001111;
4'd8:{a,b,c,d,e,f,g}=7'b0000000;
4'd9:{a,b,c,d,e,f,g}=7'b0000100;
default:{a,b,c,d,e,f,g,}=7'bx;
endcase
end
endmodule
数字逻辑 Verilog HDL 七段数码管
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2010-11-16
19:09:39
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收藏 417KB RAR 举报
LED.rar （67个子文件） 
LED.asm.rpt 7KB LED.vwf 6KB
wave2.JPG 193KB LED.map.eqn 2KB LED.done 26B cmp_state.ini 2B LED.tan.rpt 8KB LED.map.summary 365B pin.JPG 194KB
db LED.sgdiff.cdb 831B LED.hif 413B LED.rtlv_sg.cdb 1KB LED.tan.qmsg 3KB LED.signalprobe.cdb 539B LED.cbx.xml 85B LED.sim.hdb 2KB LED.cmp.hdb 5KB LED.map.cdb 1KB LED.pre_map.cdb 1KB LED.fnsim.cdb 987B LED.db_info 135B LED_sim.qrpt 0B LED.syn_hier_info 0B LED.cmp.tdb 2KB LED.eds_overflow 2B LED.sld_design_entry.sci 134B LED.asm.qmsg 1KB LED.(0).cnf.hdb 416B LED.rtlv.hdb 5KB LED.sim.vwf 7KB LED.psp 0B LED.sld_design_entry_dsc.sci 134B LED.hier_info 390B LED.sgdiff.hdb 6KB LED.map.hdb 5KB LED.fnsim.hdb 6KB LED.fit.qmsg 6KB LED.rtlv_sg_swap.cdb 157B LED.(0).cnf.cdb 1KB LED.sim.rdb 1KB LED.cmp.rdb 3KB LED.pre_map.hdb 6KB LED.cmp0.ddb 17KB LED.sim.qmsg 1KB LED.map.qmsg 2KB LED.eco.cdb 140B LED.cmp.cdb 3KB LED_cmp.qrpt 0B LED.bsf 3KB LED.fit.eqn 3KB LED.sof 137KB LED.flow.rpt 3KB LED.pin 29KB LED.fit.rpt 62KB LED.fit.summary 427B talkback LED.map.talkback.xml 9KB LED.sim.talkback.xml 2KB LED.v 583B LED.qsf 2KB LED.tan.summary 707B LED.qws 654B LED.map.rpt 13KB
code.txt 583B LED.pof 512KB LED.qpf 942B LED.sim.rpt 4KB wave.JPG 177KB资源评论
