Verilog HDL BCD七段译码器

//-----------------------------------------------------------------------------------
// DESCRIPTION   :   BIN to seven segments converter
//                   segment encoding
//                        a
//                      +---+ 
//                    f |   | b
//                      +---+  <- g
//                    e |   | c
//                      +---+
//                        d
//                  Enable (EN) active                : high
//                  Outputs (data_out) active         : low
//-----------------------------------------------------------------------------------



module bin27seg (data_in ,EN ,data_out );

input [3:0] data_in ;

input EN ;

output [6:0] data_out ;
reg [6:0] data_out ;


always @(data_in or EN )
begin
data_out = 7'b1111111;
if (EN == 1)