Zynq-7000 EPP
Packaging and Pinout
Advance Product Specification
UG865 (v1.0) May 8, 2012
Zynq-7000 EPP Packaging Guide www.xilinx.com 2
UG865 (v1.0) May 8, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
05/08/12 1.0
Initial Xilinx release.
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UG865 (v1.0) May 8, 2012
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Package Overview
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device/Package Combinations and Maximum I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Compatibility Between Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 2: Zynq-7000 EPP Package Files
About ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ASCII Pinout Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 3: Device Diagrams
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Zynq-7000 EPP Device Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 4: Mechanical Drawings
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
CLG400 Wire-Bond Chip-Scale BGA (XC7Z010 and XC7Z020)(0.8 mm Pitch) . . . . . . . . . . . . . . . . . . 49
CLG484 Wire-Bond Chip-Scale BGA (XC7Z020)
(0.8 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chapter 5: Thermal Specifications
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Thermal Management Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Some Thermal Management Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Support for Compact Thermal Models (CTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Soldering Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
References for Chapter 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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Chapter 6: Package Marking
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Appendix A: Recommended PCB Design Rules
BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Appendix B: Heat Sink Guidelines for Lidless Flip-Chip Packages
Heat Sink Attachments for Lidless FCBGA (FB/FBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Types of Heat Sink Attachments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Reasons for Thermal Interface Material. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Thermal Material Handling Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Appendix C: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Zynq-7000 EPP Packaging Guide www.xilinx.com 5
UG865 (v1.0) May 8, 2012
Chapter 1
Package Overview
Summary
This chapter covers the following topics:
• Introduction
• Device/Package Combinations and Maximum I/Os
• Pin Definitions
• Pin Compatibility Between Packages
• Die Level Bank Numbering Overview
Introduction
This section describes the pinouts for the Zynq™-7000 Extensible Processing Platform (EPP)
available in 0.8 mm pitch wire bond and various 1.0 mm pitch flip-chip and fine-pitch BGA
packages.
Package inductance is minimized as a result of optimal placement and even distribution as
well as an optimal number of Power and GND pins.
All packages are available as Pb-free (additional G in package name) with selected packages
including a Pb-only option.
All of the Zynq-7000 EPP devices supported in a particular package are pinout compatible.
Pins that are not available in a device but are not available in smaller device with a
compatible package are listed as “No Connects”.
The Zynq-7000 EPP contains a large number of fixed and flexible I/O. The Zynq-7000 EPP
has a constant 130 pins dedicated to memory interfaces (DDR I/O), multiplexed peripherals
(MIO), and control. Programmable logic provides additional pins for SelectIO™ resources
(SIO) and multi-gigabit serial transceivers (GTX) that scale by device as well as f ixed pins for
configuration and analog-to-digital conversion (XADC). SIO can be used to extend the MIO
to further leverage the fixed peripherals of the processing system (PS).
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