zynq7000芯片资料介绍

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zynq7000芯片资料介绍
RA XILINX Zyng-7000 SoC Data Sheet: Overview Table 1: Zyng-7000 and Zyng-7000S Socs(Cont'd) Device Name Z7007z7012sz701427010 Z-7015 Z-7020 Z-7030 Z-7035 Z-7045 Z-7100 Part Number XC7Z0O7S XC7Z012S XC7Z014S XC7Z010 XC7Z015 XC7Z020 XC7Z030 XC7Z035 XC7Z045 XC7Z100 Xilinx 7 Series Artix(R-7 Artix Programmable Logic Artix-7 Artix-7 KintexR-7 Kintex-7 Kintex-7 Kintex-7 FPGA Equivalent FPGA PGA FPGA FPGA FPGA Programmable Logic Cells 55K 65K 28K 74K 125K 275K 350K Look-Up Tables(LUTS)14,400 34,400 40,600 17,600 46,200 53200 78,600 171.90 218,600 277,400 Flip-Flops 28800 68800 81200 35,200 92,400 106,400 157200343800437,200 554,800 Block RAM 1.8Mb 2.5Mb 3.8Mo 2.1Mb 3.3Mb 4.9Mb 9. 3 Mb 17.6 Mb 19.2 Mb 265Mb 36 Kb Blocks (50) (72) (107) (60) (95) (140) (265) 500) (545) (755) 120 17 160 400 900 9o0 是| Performance 131 187 100 200 276 593 1,334 1.334 2.622 (SymmetrIc FIR) GMACs GMACs GMACsGMACs GMACs GMACS GMACS GMACs GMACs GMACs PCI Express Root Complex or Gen2 x4 Gen2 x4 Gen2 x8Gen2 X8Gen2X8 Analog Mixed Signal 2X 12 bit, MSPS ADCs with up to 17 Differential Inputs AMS)/XADC Security(2) AES and SHa 256b for Boot Code and Programmable Logic Configuration, Decryption and authentication 1. Restrictions apply for CLG225 package Refer to the UG585, Zyng- 7000 Soc Technical Reference Manual(TRm)for details 2. Security is shared by the Processing System and the Programmable Logic 3. Reter to PG054, 7 Series FPGAs Integrated Block for PCI Express for PCI EXpress support in specitic devices DS190(111.1)Juy2,2018 www.xilinx.com Product Specification &A XILINX Zyng-7000 SoC Data Sheet: Overview Table 2: Device-Package Combinations: Maximum I/Os and GTP and gtx transceivers Package(1) CLG225 CLG400 CLG484 cLG485(2) SBG4852) Size 13x 13 mm 7x17 mm 19x 19 mm 19x19 mm 19 x 19 mm Ball Pitch 0.8mm 0.8mm 0.8mm 0.8mm 0.8mm Transceiver Speed(max) 6.25Gb/s 6.6 Gb/s SelectIo SelectIo SelectIo SelectIo SelectIo Device PS VO(3) HR(4/ HP(5 PS W/O() PS vO(3) PS W/O(3)GTP PS 1/O(S)GTX HR(4) HP(5) HR(4)HP(5) HR(4) HP(5) HR(4)HP(5) C7Z007S 128 100 XC7Z012S 28 150 XC7Z014S 128 125 128 200 XC7Z010 84 54 128100 XC7Z015 128 150 XC7Z020 128 125 128 200 XC7Z030 128 100 XC7Z035 XC7Z045 XC77100 Notes 1. All packages listed are Pb-free SBG485 with exemption 15). Some packages are available with a Pb option 2. The Z-7012S and z-7015 devices in the clG485 package and the z- 7030 device in the sBG485 package are pin-to-pin compatible 3. Ps I/O count does not include dedicated DDR calibration pins 4. HR= High Range 1/0 with support for 1O voltage frorm 1.2V to 3. 3V 5. HP= High Pertormance / o with support for l/O voltage from 1.2V to 1.8V. Table 3: Device-Package Combinations: Maximum 1/Os and GTP and GTX Transceivers(Cont'd) Package (1) FBG484 FBG676 FFG676 FFG900 FFG1156 23 x 23 mm 27 x 27 mm 27x 27 mm 31 x 31 mm 35x 35 mm Ball Pitch 1.0mm 1.0mm 1.0 mm 1.0 mm 1.0mm Transceiver Speed(max) 6.6 Gb/s 66Gb/ 12.5 Gb/s 12.5 Gb/s 10. 3 Gb/s SelectIo SelectIo Selecto SelectIO SelectIo Device PS WO(2)GTX PS VO(2)GTX PS W/O(2)GTX PS VO(2) GTX PS WO(2)GTX HR(3) HP(4) HR(3) HP(4) HR 3 HP(4) HR 3)HP(4) HR③)HP4 XC7Z007S XC7Z012S XC7Z0 14S XC7Z010 XC7Z015 XC7Z020 XC7Z030 128 128 4100150 128 4100150 XC7Z035 28 81001501288100150128 6212150 XC7Z045 128 8100150 128 8100150128 16212150 XC7Z100 1281621215012816250150 Notes: 1. All packages listed are Pb-free(FBG and FFG with exemption 15). Some packages are available with a pb option 2. Ps l/o count does not include dedicated ddr calibration pins 3. HR= High Range l/O with support for lO voltage from 1.2V to 3. 3V 4. HP= High Performance vO with support for v/O voltage from 1. 2V to 1. 8V DS190(111.1)Juy2,2018 www.xilinx.com Product Specification 4 RA XILINX Zyng-7000 SoC Data Sheet: Overview Zyng-7000 Family Description The Zyng-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 family allows designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the Zynq- 7000 family contains the same PS, the PL and l/0 resources vary between the devices. As a result, the Zyng-7000 and Zyng-7000S SoCs are able to serve a wide range of applications including Automotive driver assistance, driver information and infotainment Broadcast camera Industrial motor control, industrial networking, and machine vision iP and smart camera LTE radio and baseband Medical diagnostics and imaging Multifunction printers video and night vision equipment The Zyng- 7000 architecture enables implementation of custom logic in the Pl and custom software in the Ps. It allows for he realization of unique and differentiated system functions. The integration of the Ps with the PL allows levels of performance that two-chip solutions(e.g, an ASSP with an FPGA) cannot match due to their limited lO bandwidth, latency, and power budgets Xilinx offers a large number of soft IP for the Zynq-7000 family. Stand-alone and Linux device drivers are available for the peripherals in the PS and the PL. The vivado@ Design Suite development environment enables a rapid product development for software, hardware, and systems engineers. Adoption of the ARM-based Ps also brings a broad range of third-party tools and iP providers in combination with Xilinx's existing PL ecosystem The inclusion of an application processor enables high-level operating system support, e.g., Linux. Other standard operating systems used with the Cortex-A9 processor are also available for the Zyng-7000 family The Ps and the PL are on separate power domains, enabling the user of these devices to power down the PL for power management if required. the processors in the Ps always boot first, allowing a software centric approach for PL configuration. PL configuration is managed by software running on the CPU, so it boots similar to an ASSP DS190(111.1)Juy2,2018 www.xilinx.com Product Specification 5 RA XILINX Zyng-7000 SoC Data Sheet: Overview Figure 1 illustrates the functional blocks of the Zyng-7000 architecture. For more information on the functional blocks, see UG585, Zyng- 7000 Soc Technical Reference Manual yng-7000 SoC Processing System Peripherals Clock Application Processor Unit Reset SWDT USB Generation FPU and NEoN Engine FPU and NEoN Engine TTC USB 2X USB ARM Cortex-A9 ARM Cortex-A9 MN MMU GigE L2x Gigl System CPU CPU GigE 2X SD Level 32 KB 32 KB 32 KB 32 KB ache D-Cache I-Cache D-Cache SDIO IRQ Regs GIC Snoop Controller, AWDT, Timer SDIO GPIO dma 8 512 KB L2 Cache Controller UART Channel 丿ART CAN OCM256K CAN Interconnect SRAM 12C 12C Me SPI Central Interfaces SPI Interconnect DDR2/3 Core Sight M DDR3L Interfaces Components LPDDR2 Controller SRAM/ NOR DAP ONFI 1.0 NAND Devc Programmable Logic to Q-SP Memory Interconnect CTRL EMIO ⅩADC General-Purpose DMA IRQ Config High-Performance Ports ACP 12-Bit ADC Ports Sync AES/ SHA Programmable Logic SelectIo Notes: Resources 1)Arrow direction shows control( master to slave) 2)Data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, Custom 3)Dashed line box indicates 2nd processor in dual-core devices DS190_01070218 Figure 1: Architectural Overview DS190(111.1)Juy2,2018 www.xilinx.com Product Specification 6 RA XILINX Zyng-7000 SoC Data Sheet: Overview Processor System Description As shown in Figure 1, the Ps comprises four major blocks Application processor unit(APU) Memory interfaces 10 peripherals(IOP) Interconnect Application Processor Unit(APU The key features of the aPu include Dual-core or single-core ARM Cortex-A9 MPCores Features associated with each core include ·2.5DMPs/MHz Operating frequency range 2-7007S/27012S/z7014s( wire bond;:Upto667MHz(-1);766MHz(-2) z-7010/2-7015/2z-7020( wire bond):Upto667MHz(-1);766MHz(-2):866MHz(-3) 2703027035/27045( flip-chip):667MHz(-1);800MHz(2);1GHz(-3) z7100( flip-chip):667MHz(-1);800MHz(-2) Ability to operate in single processor, symmetric dual processor, and asymmetric dual processor modes Single and double precision floating point: up to 2.0 MFLOPS/MHz each Neon media processing engine for sIMd support Thumb-2 support for code compression Level 1 caches(separate instruction and data, 32 KB each 4-way set-associative Non-blocking data cache with support for up to four outstanding read and write misses each Integrated memory management unit(MMU) TrustZone for secure mode operation Accelerator coherency port(ACP) interface enabling coherent accesses from PL to CPU memory space Unified Level 2 cache(512 KB) 8-way set-associative TrustZone enabled for secure operation Dual-ported, on-chip RAM(256 KB Accessible by CPU and programmable logic(PL) Designed for low latency access from the CPU 8-channel DMA Supports multiple transfer types: memory-to- memory, memory-to-peripheral, peripheral-to- memory, and scatter-gather 64-bit AXI interface, enabling high throughput DMA transfers 4 channels dedicated to pl Trustzone enabled for secure operation Dual register access interfaces enforce separation between secure and non-secure accesses DS190(111.1)Juy2,2018 www.xilinx.com Product Specification RA XILINX Zyng-7000 SoC Data Sheet: Overview Interrupts and timers General interrupt controller(GIC) Three watch dog timers(WDT)(one per CPU and one system WDT Two triple timers/counters TTC) Core Sight debug and trace support for Cortex-A9 Program trace macrocell(PTM)for instruction and trace Cross trigger interface(CTI)enabling hardware breakpoints and triggers Memory Interfaces The memory interface unit includes a dynamic memory controller and static memory intertace modules. The dynamic memory controller supports DDR3, DDR3L, DDR2, and LPDDR2 memories. The static memory controllers support a NAnD flash interface, a Quad-SPI flash interface, a parallel data bus, and a parallel nor flash interface Dynamic Memory Interfaces The multi-protocol DDR memory controller can be configured to provide 16-bit or 32-bit-wide accesses to a 1 GB address space using a single rank configuration of 8-bit, 16-bit or 32-bit DRAM memories. ECC is supported in 16-bit bus access mode. The PS incorporates both the dDR controller and the associated PHY, including its own set of dedicated /Os. Speed of up to 1333 Mb/s for DDR3 is supported The DDR memory controller is multi-ported and enables the processing system and the programmable logic to have shared access to a common memory. The dDR controller features four AXi slave ports for this purpose One 64-bit port is dedicated for the ARM CPU(s)via the L2 cache controller and can be configured for low latency Two 64-bit ports are dedicated for PL access One 64-bit AXI port is shared by all other aXl masters via the central interconnect Static Memory Interfaces The static memory interfaces support external static memories 8-bit SRAM data bus supporting up to 64 MB 8-bit parallel NOR flash supporting up to 64 MB oNFi 1.0 NAND flash support with 1-bit ECC 1-bit SPL, 2-bit SPl, 4-bit SPl(quad-SPD, or two quad-SPI (8-bit)serial NOR flash 1o Peripherals(IOP) The loP unit contains the data communication peripherals. Key features of the lOP include Two 10/100/1000 tri-mode Ethernet MAc peripherals with IEEE Std 802. 3 and IEEE Std 1588 revision 2.0 support Scatter-gather dma capability Recognition of 1588 rev. 2 PTP frames Supports an external PHY interface TWO USB 2.0 OTG peripherals, each supporting up to 12 endpoints Supports high-speed and full-speed modes in Host, device, and On-The-Go configuration Fully USB 2.0 compliant, Host, and Device IP core Uses 32-bit AHb dMa master and ahb slave interfaces Provides an 8-bit ulpi external phy interface Intel eHci compliant Usb host controller registers and data structures DS190(111.1)Juy2,2018 www.xilinx.com Product Specification RA XILINX Zyng-7000 SoC Data Sheet: Overview Two full can 2.0B compliant can bus interface controllers CAN 2.0-B standard as defined by bOSCH Gmbh lso118981-1 An external PhY interface Two SD/SDIo 2.0 compliant sd/ sdio controllers with built-in dma Two full-duplex SPI ports with three peripheral chip selects TWO UARTs Two master and slave 12C interfaces Up to 118 GPIO bits Using the Trustzone system, the two Ethernet, two SDIO, and two USB ports(all master devices)can be configured to be secure or non-secure The ioP peripherals communicate to external devices through a shared pool of up to 54 dedicated multiuse I/0(MIO) pins Each peripheral can be assigned one of several pre-defined groups of pins, enabling a flexible assignment of multiple devices simultaneously. although 54 pins are not enough for simultaneous use of all the o peripherals, most lOP interface signals are available to the PL, allowing use of standard Pl io pins when powered up and properly configured. All MIO pins support 1.8V HSTL and Lvcmos standards as well as 2.5V/3.3v standards Interconnect The aPU, memory interface unit, and the loP are all connected to each other and to the pl through a multilayered arm AMBA AXI interconnect. The interconnect is non-blocking and supports multiple simultaneous master-slave transactions. The interconnect is designed with latency sensitive masters, such as the ARM CPU, having the shortest paths to memory and bandwidth critical masters, such as the potential PL masters having high throughput connections to the slaves with which they need to communicate Traffic through the interconnect can be regulated through the Quality of Service(Qos) block in the interconnect. The Qos feature is used to regulate traffic generated by the cPu, dma controller, and a combined entity representing the masters in the IoP PS Interfaces PS EXternal Interfaces The Ps external interfaces use dedicated pins that cannot be assigned as PL pins. These include Clock, reset boot mode, and voltage reference Up to 54 dedicated multiuse 0(MIO) pins, software-configurable to connect to any of the internal l/o peripherals and static memory controllers 32-bit or 16-bit DDR2/DDR 3/DDR3L/LPDDR2 memories MIO Overview The function of the Mio is to multiplex access from the Ps peripheral and static memory interfaces to the PS pins as defined in the configuration registers. There are up to 54 pins available for use by the lOP and static memory interfaces in the PS Table 4 shows where the different peripherals pins can be mapped. a block diagram of the MIo module is shown in Figure 2 If additional lo pins beyond the 54 are required, it is possible to route these through the Pl to the v0 associated with the PL. This feature is referred to as extendable multiplexed IO(EMIO) Port mappings can appear in multiple locations. For example, there are up to 1 2 possible port mappings for CAN pins.The PS Configuration Wizard(PCw) tool should be used for peripheral and static memory pin mapping DS190(111.1)Juy2,2018 www.xilinx.com Product Specification &A XILINX Zyng-7000 SoC Data Sheet: Overview Table 4: MIO Peripheral Interface Mapping Peripheral Interface MIO EMIO Quad-SPI Yes N NOR/SRAM NAND USB 0.1 Yes-External phy SDIO 0.1 Y SP:0,1 Y YY 2C:0.1 CAN:Eⅹ ternal|PHY CAN: External PHY CAN: 0.1 GPIO: Up to 54 bits GPIO: Up to 64 bits GPIO GigE: 0.1 RGMI V2.0 Supports GMll, RGMII v2.0(HSTL), RGMll v13, MIl, SGMIl, and 1000BASE-Xi External Phy Programmable Logic UART: 0.1 Simple UART Full UART (TX, RX, DTR, DCD, DSR, RI, RTS and CTS) either require Only two pins(T× and Rx) Two Processing System pins(Rx and Tx) through MIO and six additional Programmable Logic pins, or Eight Programmable Logic pins Debug Trace Ports Yes- Up to 16 trace bits Yes—Upto32 trace bits Processor jTAG Yes Yes Notes: 1. Restrictions apply for the CLG225 package Go to UG585, Zyng-7000 Soc Technical Reference Manual (TRM) for details DS190(111.1)Juy2,2018 www.xilinx.com Product Specification 10

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