一种新的基于FPGA的加密技术

介绍和讨论基于FPGA的硬件技术实现分组加密算法时所采用的4种结构 及其性能.同时对5种AES侯选算法的软件实现和FPGA实现的结果和性能进行比较分 析.

一种FIR滤波器的FPGA实现

数字滤波是语音与图像处理和模式识别等应用中的一种基本的数字信号处理部件。文中提出了一种采用FPGA器件并利用窗函数 实现线性FIR数字滤波器的方案,使用Xilinx公司的XCS10 FPGA器件设计了一个8阶8位FIR滤波器,阶数和位数以及滤波器特性均可方 便地更改。

XILINX DDC_DUC

Designing DUC and DDC functions can be achieved easily with FPGAs. Engineers, however, need to know how to leverage the silicon architectures and system-level tradeoffs that result in the lowest cost implementation. Significant area savings can be achieved with careful choice of clock speed and evaluation of different filter architectures to realize the same function.

半带并行FIR滤波器

&VirtexTM-4 DSP48 Slice
&'
FIR

Virtex-4
&'*FIR
&'*

&'*&'
&'*RAM
4
FIR
RAM
3

FIR

&'*&& System Generator in DSP
VHDL
Verilog
&'*

FPGA开发全攻略——基础篇和技巧篇

帮助工程师设计的FPGA电子书，以VHDL 或者Verilog 语言来表达设计意图、以FPGA 做为硬件载体、以计算机为设计开发工具，以EDA 软件为开发环境、以SoC、IP 等为综合设计的方法。

短波接收机中数字AGC的FPGA设计与实现

根据短波接收机对自动增益控制(AGC)电路的增益调节范围的要求，本文从AGC的基本原理和实现方法出发，给出一种前馈式数字AGC算法。讨论了该算法的设计结构和各个参数的设置方法，并给出了用FPGA实现该算法的技巧。仿真结果表明，该算法使复杂的数字式AGC可以很容易的实现，并且节省了硬件资源。

FPGA器件实现乘法器

Stratix® II, Stratix, Stratix GX, Cyclone™ II, and Cyclone devices have dedicated architectural features that make it easy to implement highperformance multipliers. Stratix II, Stratix, and Stratix GX devices feature embedded high-performance multiplier-accumulators (MACs) in dedicated digital signal processing (DSP) blocks. DSP blocks can operate at data rates above 300 million samples per second (MSPS), making Stratix II, Stratix, and Stratix GX devices ideal for high-speed DSP applications. Cyclone II devices have embedded multiplier blocks for DSP. In addition to the dedicated DSP blocks, designers can also use the Stratix II, Stratix, and Stratix GX devices’ TriMatrix™ memory blocks to implement high-performance soft multipliers of variable depths and widths. For example, designers can useTriMatrix memory blocks as lookup tables (LUTs) that contain partial results from multiplication of input data with coefficients. Cyclone II and Cyclone devices have M4K memory blocks which can be used as LUTs to implement variable depth/width high-performance soft multipliers for low cost, high volume DSP applications.

A/D转换器测试技术及发现ADC中丢失的代码

A/D转换器的量化噪声、丢失位、谐波失真以及其他非线性失真特性都可以通过分析转换器输出的频谱分量来判定。 确定由上述这些非线性特性所引起的转换器性能的下降并不困难，因为这些都呈现为A/D转换器的输出噪声中的一些杂散频谱分量以及背景噪声的增加。

altera Nios II 处理器参考手册

Chapter 5, SDRAM Controller with Avalon Interface ■ Chapter 6, DMA Controller with Avalon Interface ■ Chapter 7, PIO Core With Avalon Interface ■ Chapter 8, Timer Core with Avalon Interface ■ Chapter 9, JTAG UART Core with Avalon Interface ■ Chapter 10, UART Core with Avalon Interface ■ Chapter 11, SPI Core with Avalon Interface ■ Chapter 12, EPCS Device Controller Core with Avalon Interface ■ Chapter 13, Common Flash Interface Controller Core with Avalon Interface ■ Chapter 14, System ID Core with Avalon Interface ■ Chapter 15, Character LCD (Optrex 16207) Controller with Avalon Interface ■ Chapter 16, Mutex Core with Avalon Interface

基于FPGA的FIR抽取滤波器设计

用FPGA实现抽取滤波器比较复杂，主要是因为在FPGA中缺乏实现乘法运算的有效结构，现在，FPGA中集成了硬件乘法器，使FPGA在数字信号处理方面有了长足的进步。本文介绍了一种采用Xilinx公司的XC2V1000实现FIR抽取滤波器的设计方法。