################################################################################
# Vivado (TM) v2018.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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JESD204B发送模块代码 (436个子文件)
xsim.ini.bak 21KB
elaborate.bat 934B
compile.bat 832B
simulate.bat 795B
xsim_14.c 1.33MB
xsim.dbg 312KB
jesd204_0.dcp 701KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
simulate.do 329B
simulate.do 324B
simulate.do 324B
elaborate.do 201B
simulate.do 195B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 13.05MB
run.f 3KB
run.f 3KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 64B
xsim.ini 21KB
xsim.ini 98B
vivado.jou 957B
webtalk_2496.backup.jou 918B
webtalk.jou 918B
vivado.log 41KB
webtalk_2496.backup.log 1KB
webtalk.log 1KB
elaborate.log 579B
xsimkernel.log 225B
xsimcrash.log 0B
xvlog.log 0B
compile.log 0B
simulate.log 0B
jesd204_0_ex.lpr 290B
xsim.mem 13.49MB
xsim_8.win64.obj 1.3MB
xsim_10.win64.obj 1.29MB
xsim_11.win64.obj 1.25MB
xsim_9.win64.obj 1.21MB
xsim_7.win64.obj 1.21MB
xsim_1.win64.obj 1.2MB
xsim_2.win64.obj 1.18MB
xsim_12.win64.obj 1.16MB
xsim_0.win64.obj 1.09MB
xsim_4.win64.obj 1.08MB
xsim_5.win64.obj 1.02MB
xsim_3.win64.obj 1.01MB
xsim_6.win64.obj 956KB
xsim_14.win64.obj 916KB
xsim_13.win64.obj 12KB
elab.opt 206B
xelab.pb 975B
xvlog.pb 16B
demo_tb_vlog.prj 3KB
vlog.prj 3KB
vhdl.prj 78B
xsim.reloc 14.71MB
xil_defaultlib.rlx 9KB
xsim.rlx 1KB
xsim.rtti 648B
jesd204_0_register_decode.sdb 78KB
demo_tb.sdb 53KB
jesd204_0_phy_gt_init.sdb 40KB
jesd204_0_phy_gt_@r@x_@s@t@a@r@t@u@p_@f@s@m.sdb 35KB
jesd204_0_block.sdb 33KB
jesd204_0_phy_gt_@g@t.sdb 31KB
jesd204_0_phy_gt_multi_gt.sdb 26KB
jesd204_0_phy_block.sdb 26KB
jesd204_0_phy_gt.sdb 22KB
jesd204_0_slave_attachment.sdb 22KB
jesd204_0_phy_gt_@t@x_@s@t@a@r@t@u@p_@f@s@m.sdb 22KB
jesd204_0_phy.sdb 16KB
jesd204_0_phy_support.sdb 15KB
jesd204_0_address_decoder.sdb 13KB
jesd204_0_example_design.sdb 11KB
jesd204_0_support.sdb 11KB
jesd204_0_sig_gen.sdb 9KB
jesd204_0_phy_gtwizard_0_common.sdb 6KB
jesd204_0_axi_lite_ipif.sdb 6KB
jesd204_0.sdb 5KB
glbl.sdb 4KB
jesd204_0_reset_block.sdb 4KB
jesd204_0_transport_layer_mapper.sdb 3KB
jesd204_0_counter_f.sdb 3KB
jesd204_0_phy_gt_sync_block.sdb 3KB
jesd204_0_phy_gt_common_wrapper.sdb 2KB
jesd204_0_clocking.sdb 2KB
jesd204_0_phy_gt_cpll_railing.sdb 2KB
jesd204_0_pselect_f.sdb 2KB
jesd204_0_phy_sync_block.sdb 2KB
jesd204_0.sh 10KB
jesd204_0.sh 6KB
jesd204_0.sh 6KB
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资源评论
- 花开半夏3212023-05-16对于学协议内容没什么用
- 阿西吧1202019-06-02还可以的啊。
- hitalf2019-01-31下下来学习一下
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