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::****************************************************************************
:: ____ ____
:: / /\/ /
:: /___/ \ / Vendor : Xilinx
:: \ \ \/ Version : 3.92
:: \ \ Application : MIG
:: / / Filename : readme.txt
:: /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
:: \ \ / \ Date Created : Fri Feb 06 2009
:: \___\/\___\
::
:: Device : Spartan-6
:: Design Name : DDR/DDR2/DDR3/LPDDR
:: Purpose : Information about par folder
:: Reference :
:: Revision History :
::****************************************************************************
This folder has the batch files to synthesize using XST or Synplify Pro and
implement the design either in "Command Line Mode" or in "GUI Mode".
Steps to run the design using the ise_flow (batch mode):
1. Executing the "ise_flow.bat" file synthesizes the design using XST or
Synplify Pro and does implement the design.
a. First it removes the XST/Synplify Pro report files, implementation
files, supporting scripts, the generated chipscope designs (if
enabled) and the ISE project files (if exist any on previous runs)
b. Synthesizes the design either with XST or Synplicity
c. Implements the design with ISE.
2. After the design is run, it creates ise_flow_results.txt file that will have
the ISE log information.
Steps to run the design using the create_ise (GUI mode - for XST cases only):
1. This file will appear for XST cases only.
2. On executing the "create_ise.bat" file creates "test.xise" project file
and set all the properties of the design selected.
3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file.
4. In Linux operating systems, test.xise project can be invoked by executing the command
'ise test.xise' from the terminal.
Other files in PAR folder :
* "example_top.ucf" file is the constraint file for the design.
It has clock constraints, location constraints and IO standards.
* "mem_interface_top.ut" file has the options for the Configuration file
generation i.e. the "example_top.bit" file to run in batch mode.
* "rem_files.bat" file has all the ISE/Synplify Pro generated report files,
implementation files, supporting scripts, the generated chipscope designs
(if enabled) and the ISE project files.
* "set_ise_prop.tcl" file has all the properties that are to be
set in GUI mode.
* "ise_run.txt" file has synthesis options for the XST tool.
This file is used for batch mode.
* "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to
generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the
EDIF/NGC files, you must execute the following commands before starting
synthesis and PAR.
coregen -b ila_coregen.xco
coregen -b icon_coregen.xco
coregen -b vio_coregen.xco
Note : When you generate the design using "Debug Signals for Memory Controller"
option Enable, the above mentioned ChipScope coregen commands are printed
into ise_flow.bat and create_ise.bat files. The example_top rtl file
will have the design debug signals portmapped to vio and icon
ChipScope modules.
* At the start of a Chip Scope Analyzer project, all of the signals in
every core have generic names. "example_top.cdc" is a file that contains
all the signal names of all cores. Upon importing this file, signal names are
renamed to the specified names in "example_top.cdc" file. This file will work
for the generated designs from MIG. If any of the design parameter values
are changed after generating the design, this file will not work.
For Multiple Controller designs, signal names provided in CDC file are of
the controller that is enabled for Debug in the GUI.
synth folder:
1. mem_interface_top_synp.sdc
2. script_synp.tcl
3. example_top.prj
4. example_top.lso
mem_interface_top_synp.sdc and script_synp.tcl files are being used by
Synplify Pro and example_top.prj and example_top.lso are being used by XST.
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基于spartan6 FPGA的DDR3 IP核应用 (237个子文件)
ddr3_mig.v.bak 39KB
infrastructure.v.bak 11KB
ddr3_user_ctrl.v.bak 7KB
rem_files.bat 8KB
rem_files.bat 8KB
ise_flow.bat 4KB
ise_flow.bat 4KB
isim.bat 3KB
isim.bat 3KB
create_ise.bat 3KB
create_ise.bat 3KB
makeproj.bat 28B
makeproj.bat 28B
ddr3_demo.bgn 7KB
ddr3_demo.bit 2.34MB
ddr3_demo_cs.blc 1019B
ddr3_demo.bld 4KB
ddr3_demo_debug.cdc 51KB
ila_pro_0.cdc 24KB
coregen.cgc 43KB
coregen.cgc 16KB
coregen.cgp 520B
coregen.cgp 520B
coregen.cgp 239B
ddr3_demo.cmd_log 2KB
ddr3_c4.cpj 247KB
ddr3_demo_pad.csv 27KB
sim.do 5KB
sim.do 5KB
ddr3_demo.drc 781B
ddr3_demo.gise 12KB
ila_pro_0.gise 1KB
icon_pro.gise 1KB
ddr3_mig.gise 1KB
usage_statistics_webtalk.html 217KB
par_usage_statistics.html 4KB
mcb_ui_top_summary.html 3KB
ddr3_mig_summary.html 3KB
coregen.log 5KB
coregen.log 2KB
coregen.log 2KB
webtalk.log 762B
ddr3_mig.lso 6B
ddr3_demo.lso 6B
example_top.lso 6B
netlist.lst 88B
ddr3_demo_map.map 17KB
ddr3_demo_map.mrp 64KB
ddr3_demo.ncd 1.2MB
ddr3_demo_guide.ncd 1.2MB
ddr3_demo_map.ncd 631KB
ddr3_demo_cs.ngc 2.37MB
ila_pro_0.ngc 1.29MB
ddr3_demo.ngc 977KB
icon_pro.ngc 32KB
ddr3_demo.ngd 3.33MB
ddr3_demo_map.ngm 6.52MB
ddr3_demo_cs_signalbrowser.ngo 978KB
ddr3_demo.ngr 937KB
ddr3_demo.pad 27KB
ddr3_demo.par 20KB
ddr3_demo.pcf 798KB
ug388.pdf 2.07MB
ug416.pdf 78KB
mig.prj 3KB
mig.prj 3KB
mig.prj 3KB
ddr3_mig.prj 1KB
example_top.prj 1KB
ddr3_mig.prj 1KB
ddr3_demo.prj 611B
ddr3_mig.prj 457B
ddr3_demo.projectmgr 8KB
ddr3_demo.ptwx 22KB
work.sdbl 863KB
work.sdbx 304B
mem_interface_top_synp.sdc 2KB
mem_interface_top_synp.sdc 1KB
ddr3_demo.stx 0B
ddr3_demo.syr 299KB
set_ise_prop.tcl 6KB
set_ise_prop.tcl 5KB
ddr3_mig_xmdf.tcl 3KB
isim.tcl 3KB
isim.tcl 3KB
ila_pro_0_xmdf.tcl 3KB
icon_pro_xmdf.tcl 2KB
script_synp.tcl 2KB
script_synp.tcl 1KB
create_ddr3_mig.tcl 1KB
ddr3_demo.twr 311KB
ddr3_demo.twx 372KB
ddr3_demo_pad.txt 137KB
readme.txt 6KB
readme.txt 6KB
readme.txt 5KB
readme.txt 5KB
ddr3_mig_flist.txt 5KB
log.txt 3KB
log.txt 3KB
共 237 条
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