数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integrated RTL circuit which contains 3 module FILTER, ERR_DECISION, ADJUST hope useful for all.
数字均衡器的FPGA实现（VHDL）
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2009-12-12
11:55:46
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收藏 75KB RAR 举报 
equlizer vhdl.rar （27个子文件） 
filter3_coef.vhd 5KB adjust.vhd 2KB filter_coef.vhd 4KB s_term2.vhd 2KB equ_pak.vhd 14KB p_s.vhd 2KB filter_con.vhd 3KB s_term1.vhd 1KB mult2.vhd 2KB
adjust.txt 2KB
数字均衡器顶层文件.bmp 822KB cmplcode2.vhd 908B shift_3.vhd 1KB s_term3.vhd 2KB mult3.vhd 2KB filter_add.vhd 2KB adjust2_mult.vhd 4KB filter_shift.vhd 2KB accumulator.vhd 1KB adjust3_mult.vhd 4KB filter.vhd 4KB 说明.txt 392B adjust_con.vhd 2KB err_decision.vhd 4KB adjust1_mult.vhd 4KB adjust_cons.txt 2KB filter_coef1.vhd 3KB
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