################################################################################
# Vivado (TM) v2017.4 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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Vivaod FFT IP核调试例子
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Vivaod FFT IP核调试例子,对8点[0 1 2 3 4 5 6 7]进行FFT 变换,Vivado仿真结果和matlab仿真结果一致。
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Vivaod FFT IP核调试例子 (196个子文件)
xsim.ini.bak 19KB
elaborate.bat 1KB
compile.bat 980B
simulate.bat 792B
runme.bat 229B
xsim_3.c 147KB
xsim.dbg 16KB
xfft_0.dcp 541KB
xfft_0.dcp 540KB
xfft_0.dcp 540KB
xfft_0.dcp 529KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
simulate.do 582B
simulate.do 567B
simulate.do 567B
elaborate.do 447B
simulate.do 189B
wave.do 12B
wave.do 12B
wave.do 12B
wave.do 12B
simulate.do 11B
xsimk.exe 2.36MB
run.f 2KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 65B
modelsim.ini 96KB
xsim.ini 19KB
xsim.ini 19KB
xsimSettings.ini 741B
webtalk_12448.backup.jou 777B
webtalk.jou 776B
vivado.jou 665B
ISEWrap.js 7KB
rundef.js 1KB
runme.log 78KB
runme.log 74KB
runme.log 73KB
elaborate.log 16KB
webtalk_12448.backup.log 846B
webtalk.log 845B
xsimcrash.log 360B
xvlog.log 328B
compile.log 328B
xsimkernel.log 326B
simulate.log 50B
xvhdl.log 0B
project_1.lpr 290B
xsim.mem 285KB
xsim_0.win64.obj 1.05MB
xsim_1.win64.obj 744KB
xsim_2.win64.obj 646KB
xsim_3.win64.obj 101KB
elab.opt 459B
vivado.pb 102KB
xelab.pb 28KB
xvlog.pb 628B
xfft_0_utilization_synth.pb 289B
xvhdl.pb 16B
top_tb_vlog.prj 281B
top_tb_vhdl.prj 166B
vhdl.prj 101B
xsim.reloc 229KB
xsim.rlx 1KB
xil_defaultlib.rlx 435B
xfft_0_utilization_synth.rpt 8KB
.vivado.begin.rst 188B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
xsim.rtti 468B
top.sdb 6KB
glbl.sdb 4KB
top_tb.sdb 1KB
xfft_0.sh 9KB
xfft_0.sh 6KB
xfft_0.sh 6KB
xfft_0.sh 5KB
xfft_0.sh 5KB
xfft_0.sh 5KB
xfft_0.sh 5KB
ISEWrap.sh 2KB
runme.sh 1KB
xsim.svtype 35B
xsim.svtype 8B
xfft_0.tcl 8KB
xsim_webtalk.tcl 4KB
cmd.tcl 464B
top_tb.tcl 460B
xfft_v9_0_changelog.txt 8KB
README.txt 3KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
共 196 条
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