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LPDDR5信号完整性研究.pdf

DDR5

信号完整性

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本文介绍了使用1抽头DFE（判决反馈均衡）的LPDDR5 SoC DRAM PoP（封装在封装上）系统的SI（信号完整性）分析。系统以6.4 Gbps的速度运行，SS拐角处为0.47V VDDQ。 DFE减轻了基于反射的ISI，并提高了眼睛孔径。 DFE已广泛应用于串行差分接口，如USBSS和PCIe，但其在LPDDR5并行单端接口中的应用是新的，并提出了独特的挑战，因为JEDEC标准六边形眼罩定义了两种定时规范，即@Vref+/-0mV和@Vref+/-50mV。 Vref是用于测量眼睛张开度的眼睛中心中的参考电压。根据所分析的信道，在写入期间，最佳的1抽头DFE反馈权重为约5mV，这在Vref+/-50mV时提高了眼孔径，而不会降低Vref+/-0mV时的眼孔径。进一步增加反馈权重会导致过度均衡，导致在Vref+/-0mV时的眼睛孔径减小，即使在Vref+/-50mV时眼睛孔径仍在增加。

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DesignCon 2021

LPDDR5 (6.4 Gbps and beyond)

1-tap and multi-tap DFE Optimal

Weights for Signal Integrity

Sunil Gupta, Ph.D.

Qualcomm Technologies, Inc. (QTI)

sungupta@qti.qualcomm.com

Keywords – LPDDR5, SoC (System-on-Chip), DRAM memory

device, Signal Integrity, PoP, eye-aperture, DFE, Vref, feedback-

weight, over-equalization.

Acknowledgements: Thanks to Ted Mido of Synopsys, Inc. along

with Qualcomm Technologies, Inc.’s PHY, IO, SIPI, Package and

PCB groups.

Abstract

SI (Signal Integrity) analysis of a LPDDR5 SoC-DRAM PoP (Package-on-Package)

system using 1-tap DFE (Decision Feedback Equalization) is presented. The system was

running at 6.4 Gbps with 0.47V VDDQ at SS corner. The DFE mitigates the reflection

based ISI and results in improved eye-aperture. DFE has been extensively used in serial

differential interfaces such as USBSS and PCIe but their use in LPDDR5 parallel single-

ended interface is new and presents unique challenges as the JEDEC standard hexagonal

eye-mask defines two timing specifications, namely @Vref+/-0mV and @Vref+/-50mV.

Vref being the reference voltage in the eye center used for measuring the eye-opening.

Based on the channel analyzed, during Writes, the optimal 1-tap DFE feedback-weight was

~5mV which improved eye-aperture @Vref+/-50mV without degrading the eye-aperture

@Vref+/-0mV. Further increasing the feedback-weight resulted in over-equalization

causing the eye-aperture @Vref+/-0mV to decrease even though the eye-aperture

@Vref+/-50mV kept increasing.

Author(s) Biography

Sunil Gupta has 20 years' experience in semiconductor design and test. He has worked at

various companies, such as IBM Corp., Intel Corp. and Qualcomm Inc. He obtained his

Ph.D. in Electrical Engineering from The University of Texas at Austin. His areas of

interest are Signal and Power integrity, Circuit Design and Silicon Validation. His work

has resulted in patents, publications, and presentations at premier conferences such as

DesignCon, EMC+SIPI, EPEPS and ECTC.

1. Introduction

Mobile phones make use of PoP SoC-DRAM memory system for data transactions using

LPDDR (Low-Power Double Data Rate) interface. Another popular configuration typically

employed in automotive and tablet systems uses external DRAM. LPDDR5 is the latest

standard with maximum data rate of 6.4 Gbps.

In a communication channel, ISI (Inter-Symbol Interference) due to reflections are

encountered. DFE are employed to counter this ISI and improve signal integrity and hence

the eye-aperture. DFE are extensively used in high-speed serial interfaces of PCIe, USBSS

and Ethernet, among others but their application to LPDDR parallel interfaces is new. The

analysis presented in this paper was performed for the Write data traffic going from SoC

to DRAM.

Background information on the SoC-DRAM in a PoP configuration is covered in section

II along with basics of x16 LPDDR5 parallel interface. This section then explains the 1-tap

DFE operation which is the focus of this paper. One could have multi-tap DFE, but

practically not desirable in mobile DRAM due to power, area, and cost considerations.

Section III covers the signal integrity analysis setup. It illustrates the PoP system SI channel

with DRAM RX (receiver) DFE. Also presented are the analysis framework, JEDEC

standard eye-mask and the timing specifications and overall system timing budget

components.

Results are presented in section IV. Eye-aperture deltas of before and after DFE with

varying feedback-weights are plotted to gauge their impact and to determine the optimal

feedback-weight. Comparison eye-diagrams of before and after DFE for optimal case and

over-equalization scenarios are shown. Finally, the key takeaways of this analysis are

summarized in section V.

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