Background
With mainstream interface specifications in the 5th generation, the challenges have never
been greater for implementing standards like PCIe 5.0 [1] at 32 GT/s. Form factors in
datacenters and high-performance computing are unchanged but supporting same
platform topologies at faster data rates demands more design complexity with smaller
margins. Translating electrical specification documents to system-level simulations is
not easy and requires combinations of models for silicon, interconnect and jitter
assessment. Behavioral modeling standards like IBIS-AMI [2] provides an interoperable
format to capture specification assumptions for silicon that allows platform developers to
get a first look at their system-level simulations before silicon vendor IP models are
available, or to compare those silicon vendor IP models to electrical specifications.
Utilizing IBIS-AMI model format to support a top-down, behavioral design
methodology, the static electrical specification documents can be converted to executable
behavioral models for end-to-end system level simulation. First, the hundreds of pages in
electrical specification will be narrowed down to the relevant material for IBIS-AMI
modeling. Next, the key transmitter (Tx), receiver (Rx) and jitter components will be
captured. For Tx in PCIe 5.0, there is the 3-tap feed-forward equalizer (FFE). For Rx in
PCIe 5.0, there are continuous-time linear equalizer (CTLE), decision-feedback equalizer
(DFE) and clock-data recovery (CDR). To optimize the Rx equalization, the system
pulse response is used to minimize post-cursor ISI strength to near zero value (while
staying positive). PCIe 5.0 jitter referenced at Tx, which will be separated into Tx & Rx
components to support IBIS-AMI simulation analysis flow.
The result will be Tx & Rx IBIS-AMI models that can support low bit error ratio (BER)
simulation analysis. Equalization values and channel conditions are varied to show
performance vs. specification limits. The results are a simulation-based approach to
utilize electrical specification details. Insights can be gained in platform-level simulation
results before vendor-based models are available.
PCIe 5.0 Specification Overview
PCI Express a high performance, general purpose I/O interconnect. The 5
th
generation,
or PCIe 5.0, operates at a signal transfer rate of 32 GT/s. To support backward
compatibility, it shares many similarities to with prior generations like same connector
pinout, Tx EQ presets, Tx Voltage and Jitter parameters and same approach to Tx and Rx
testing. Some key updates moving to PCIe 5.0 are updated Rx characteristics to support
32 GT/s such as CTLE frequency tables, 3-tap DFE and CDR frequency behavior. The
informative insertion loss budget is -36 dB at 16 GHz.
Overview of simulation with IBIS-AMI
The IBIS standard was first released in 1993 through the IBIS Open Forum. The core
functionality focused on analog electrical modeling of Tx, Rx and packages. With IBIS
Version 5.0 in 2008, the algorithmic modeling interface (AMI) support was added which
expanded the modeling capability to include discrete time processing behaviors or
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glowlaw2023-07-27通过对最新PCIe5.0规范的介绍和解读，该文件使读者能够跟上行业发展的最新趋势，并掌握相关技术。
雨后的印2023-07-27该文件提供了实用的技术指南和建议，帮助读者解决了在使用过程中常见的困惑和问题。
林书尼2023-07-27该文件用简洁的语言解释了IBIS-AMI模型的原理和应用，让读者能够轻松理解并快速上手。
仙夜子2023-07-27这份文件详细介绍了基于PCIe5.0规范的IBIS-AMI模型，让读者深入了解并掌握相关知识。
稚气筱筱2023-07-27作者在文中给出了实际案例，展示了该模型在实际工程中的应用，使读者能够更好地理解其实际价值。
