PCI Express® Base Specification Revision 5.0 Version 1.0 22 May 2019
5.0-1.0-PUB-PCI Express Base Specification Revision 5.0 Version 1.0 Table of contents 1. Introduction 1.1 A Third generation l/O Interconnect. 1.2 PCI Express Link........ 90 1.3 PCI Express Fabric Topology ··········4·····:····4···: 92 1.3.1 Root Complex… 92 13.2 Endpoints…………………… 93 1.3.2.1 Legacy Endpoint Rules 93 1.3.2.2 PCI Express Endpoint rules........ ∴94 1.3.2.3 Root Complex Integrated Endpoint Rules……… 94 1.3.3 Switch 95 13.4 Root Complex Event Collector…… 1.3.5 PCI Express to PCl/PCI-X Bridge ……96 14 Hardware/ Software Model for Discovery, Configuration and Operation………… 1.5PC| Express Layering Overview...,.,..…,…,……………………….97 1.5.1 Transaction Layer….…… 9 1.5.2 Data Link Layer 1.5.3 Physical Layer.. …9 1.5.4 Layer Functions and Services 100 1.5.4.1 Transaction Layer services 100 1.5.4.2 Data Link Layer Services 101 1.5.4.3 Physical Layer services... …101 1.5.4.4 Inter-Layer Interfaces 102 1.5.4.4. 1 Transaction/ Data Link Interface 102 1.5.4.4.2 Data Link/Physical Interface 102 2. Transaction Layer Specification…… …103 2.1 Transaction Layer Overview. 103 2.1.1 Address Spaces, Transaction Types, and Usage …104 2.1.1.1 Memory Transactions. 104 2.1.1.2 1/0 Transactions ..·:·· 104 2.1.1.3 Configuration Transactions 105 2.1.1.4 Message Transactions........... ,105 2.1.2 Packet format overview 105 2.2 Transaction Layer Protocol -Packet Definition ∴107 2.2.1 Common Packet header fields 107 2.2.2 TLPs with Data Payloads-Rules...................................110 2.2.3 TLP Digest Rules 113 22.4 Routing and Addressing Rules………… 113 2.2.4.1 Address-Based Routing rules.... 113 2.2.4.2 ID Based Routing rules.......115 2.2.5 First/Last DW Byte Enables Rules... 117 2.2.6 Transaction Descriptor 2.2.6.1 Overview 119 2.2.6.2 Transaction Descriptor-Transaction ID Field........120 2.2.6. 3 Transaction Descriptor -Attributes Field 125 2.2.6.4 Relaxed Ordering and ID-Based Ordering Attributes 126 2.2.6.5 No Snoop Attribute .... 126 Page 3 5.0-1.0-PUB-PCI Express Base Specification Revision 5.0 Version 1.0 2.2.6.6 Transaction Descriptor- Traffic Class field 127 2.2.7 Memory, I/0, and Configuration Request Rules 127 2,2.7.1 TPH Rules 翻音 131 2.2.8 Message Request rules 133 2.2.8.1 INTX Interrupt Signaling -Rules 135 2.2.8.2 Power Management messages 139 2.2.8.3 Error Signaling Messages 22.84 Locked Transactions Support...…………141 2. 2.8.5 Slot Power Limit Support 142 2.2.8.6 Vendor Defined messages ……143 2.2.8.6.1 PCl-SIG-Defined VDMs 44 2.2.8.6.2 LN Messages 145 2.2.8.6. 3 Device Readiness Status(DRS)Message 146 2.2.8.6.4 Function Readiness Status Message(FRS Message …147 2.2.8.6.5 Hierarchy ID Message......... 148 2.2.8.7 Ignored Messages.... …150 2.2. 8.8 Latency tolerance Reporting(LTR)Message.. ∴150 2.2.8.9 Optimized Buffer FlushFill (OBFF)Message ...........................151 2.2.8. 10 Precision Time Measurement(PTM)Messages ..152 2.2.9 Completion Rules...... 153 2.2.10 TLP Prefix Rules ……156 2. 2.10.1 Local TLP Prefix Processing. ∴157 2.2.10.1.1 Vendor defined Local tLp Prefix…… 157 22.10.2End- End TLP Prefix Processing…………,…...….….………….:157 2.2.10.2. 1 Vendor Defined End-End tLP Prefix 2.2. 10.2.2 Root Ports with End-End TLP Prefix Supported 159 2.3 Handling of Received TLPs 160 2.3.1 Request Handling Rules.... 163 2.3.1.1 Data Return for Read Requests. ..........................................169 2.3. 2 Completion Handling Rule 175 2.4 Transaction Ordering 2.4.1 Transaction Ordering Rules 4垂 …177 2.4.2 Update Ordering and Granularity Observed by a Read Transaction. ......181 2.4.3 Update Ordering and Granularity Provided by a Write Transaction ...................182 2.5 Virtual Channel (vc) mechanism 182 2.5.1Ⅵ /irtual channel ldentification(C|D)…....…,…… 184 2.5.2 TC to VC Mapping…...….…………185 2.5.3 VC and tc rules 186 2.6 Ordering and receive Buffer Flow Control ∴187 2.6.1 Flow Control rules 188 2.6.1.1 FC Information Tracked by transmitter ∴192 2.6.1.2 FC Information Tracked by receiver 194 2.7 Data Integrity..,.,.,.,.,…,.,…,.,…,……,…,……………….198 2.7.1 ECRC Rules 198 2.7.2 Error Forwarding . 202 2.72.1 Error Forwarding Usage Model.……….………….….…..…. 202 2.7.2.2 Rules For Use of data Poisoning ∴203 2.8 Completion Timeout Mechanis 204 2.9 Link Status Dependencies.. 205 2.9.1 Transaction Layer Behavior in DL_Down Status 205 Page 4 5.0-1.0-PUB-PCI Express Base Specification Revision 5.0 Version 1.0 2.9.2 Transaction Layer Behavior in DL_Up Status 音垂音 206 2.9.3 Transaction Layer behavior during downstream Port Containment 206 3. Data Link Layer Specification... 3.1 Data Link Layer Overview 32 Data Link Control and Management State Machine…………….,.,.,.,.,…,, …210 3.2.1 Data Link Control and Management State Machine rules...........................211 3.3 Data link feature exchange 3.4 Flow Control initialization protocol 3.4.1 Flow Control initialization state Machine rules 215 3.4.2 Scaled flow control 面,垂 220 3.5 Data Link Layer Packets(DLLPs)..... 221 3.5.1 Data Link Layer Packet Rules...... 221 36 Data Integrity Mechansisms...…,.,… 227 3.6.1| ntroduction.…… 27 3.6.2 LCRC, Sequence Number, and Retry Management(TLP Transmitter) .228 3.6.2.1 LCRC and Sequence Number rules (tlp transmitter 228 3.6.2.2 Handling of received DLLS 3.6.3 LCRC and Sequence Number (TLP Receiver) 3.6.3.1 LCRC and Sequence Number rules(tlp receiver 239 4. Physical Layer Logical Block 245 4.1 Introduction 245 4.2 Logical Sub-block 245 4.2.1 Encoding for 2.5 GT/s and 5.0 GT/s Data Rates........246 4.2.1.1 Symbol Encoding 246 4.2.1.1.1 Serialization and De-serialization of data 246 4.2.1.1.2 Special Symbols for Framing and Link Management(K Codes)...... 247 4.2. 1.1.3 8b/10b Decode rules 4.2.1.2 Framing and application of Symbols to Lanes 249 4.2.1.3 Data Scrambling.............252 4.2.2 Encoding for 8.0 GT/s and Higher Data Rates ......253 4.2.2.1 Lane Level Encoding 254 4.2.2.2 Ordered set blocks 256 4.2.2.2. 1 Block Alignment. ..........................256 4.2.2.3 Data blocks 257 4.2.2.3. 1 Framing Tokens 258 4.2.2.3.2 Transmitter Framing Requirements 263 4.223.3 Receiver Framing Requirements………………………… 264 4.2.2.3.4 Recovery from Framing Errors 音垂4 266 4. 2.2.4 Scrambling 267 4.2.2.5 Precoding........ 272 4. 2.2.6 Loopback with 128b/130b Code 274 4.2.3 Link Equalization Procedure for 8.0 GT/s and Higher Data Rates....................274 4.2.3.1 Rules for transmitter coefficients 4.2.3.2 Encoding of Presets................,.,287 4.2.4 Link Initialization and Training . 2 4.2.4.1 Training Sequences 4.2.4.2 Alternate Protocol Negotiation....,.,.,,,…,,…,…,……,……,……,.298 4.24.3 Electrical Idle Sequences(E|OS)…..,… 301 Page 5 5.0-1.0-PUB-PCI Express Base Specification Revision 5.0 Version 1.0 4.2.4.4 Inferring Electrical ldle 4.2.4.5 Lane Polarity Inversion ........306 4.2.4.6 Fast Training Sequence(FTS).…… 4. 2. 4. Start of Data Stream Ordered Set (SDs Ordered Set)........ 308 4.2. 4.8 Link Error Recovery ..................309 4.2.4.9 Reset.…… 309 4.2.4.9.1 Fundamental reset 309 4.2.4.9,2 Hot reset... 310 4. 2.4.10 Link Data Rate Negotiation 4.2.4.11 Link Width and lane sequence negotiation ∴310 4.24.1.1 Required and optional Port Behavior……… 310 4.2.4.12 Lane-to-Lane de-skew 4.2.4.13 Lane Vs Link Training.... ∴312 4.2.5 Link Training and Status State Machine( LTSSM)Descriptions 31 4.2.5.1 Detect overview….……113 4.2.5.2 Polling overview 4.2.5.3 Configuration Overview 313 4.25.4 Recovery overview…….….…….….….….….….……..………113 425.5 LO Overview ……………314 4.2.5.6 LOs Overview ∴314 4.2.5.7L1 Overview,…1314 4.2.5.8L2 Overview……………… 314 4.2.5. 9 Disabled Overview. 4.25.10 Loopback Overview….........……….………………114 4.2.5.11 Hot Reset Overview 315 4.2.6 Link Training and status State Rules 315 4.2.6.1 Detect 317 4.2.6.1.1 Detect Quiet ∴317 4.2.6.1.2DetectActiveawww.318 4.2.6.2 Polling 319 4.2.6.2.1 Polling. Active......... …319 4.2.6.2.2 Polling Compliance ........320 4.2.6.2. 3 Polling Configuration 324 4.2.6.24 Polling. Speed……… 1325 4.2.6.3 Configuration 325 4.2.6.3.1 Configuration Linkwidth Start 326 4.2.631.1 Downstream lanes 326 4.2.6.3.1.2 Upstream Lanes…………… 327 4.2.6.3.2 Configuration. Lin width. Accept... 329 4.2.6.3.2.1 Downstream lanes 329 4.2.6.3.2.2 Upstream Lanes ∴30 4.2.6.3. 3 Configuration. Lanenum Accept .332 4.2.6.3.3.1 Downstream Lanes 32 4.2.6.3.3.2 Upstream Lanes………………,…,…… 333 4.2.6.3.4 Configuration Lanenum. Wait 4.2.6.341 Downstream lanes 333 4.2.6.34.2 Upstream Lanes…… ∴34 4.2.6.3.5 Configuration Complete 334 4.2.6.3.5.1 Downstream lanes 334 4.2.6.3.5.2 Upstream Lanes…… Page 6 5.0-1.0-PUB-PCI Express Base Specification Revision 5.0 Version 1.0 4.2.6.3.6 Configuration Idle 音垂音 337 4.2.6.4 Recovery 4.2. 6.4.1 Recovery. RcvrLock 340 4.2.6.4.2 Recovery. Equalization ................ 346 4.2.6.4.2.1 Downstream Lanes ,,…347 4.2.6.4.2.1.1 Phase 1 of Transmitter equalization 347 4.2.6.4.2.1.2 Phase 2 of Transmitter equalization 349 4.2.6.4.2.1.3 Phase 3 of Transmitter Equalization .................350 4.2.6.4.2.2 Upstream lanes 352 4.2.6.4.2.2.1 Phase 0 of Transmitter Equalization 352 4.2.6.4.2.2.2 Phase 1 of Transmitter Equalization 1353 4.2.6.4.2.2.3 Phase 2 of Transmitter equalization 354 4.2.6.4.2.2.4 Phase 3 of Transmitter equalization 356 4.2.6.4. 3 Recovery Speed... …2357 4.2.6.4.4 Recovery. Rcvrcfg…… 358 4.2.6.4.5 Recovery Idle.... 363 4.2.6.5L0 366 4.2.6.6L0S… 367 4.2.6.6.1 Receiver LOs 368 4.2.6.6.1.1Rx_Los. Entry…… 368 4.2.6.6.1.2RXL0s.de.368 4.2.6.6.1.3 X LOSFTS 368 4.2. 6.6.2 Transmitter los 369 4.2.6.6. 2.1 TX_LOS Entry 4.2.6.622TL0sdle 369 4.2.6.6.2.3TXL0s.FTS…369 4.2.6.7L1. 371 4.2.6.71L1. Entry.…...... 371 4.2.6.7.2L1.de.1371 4.2.68L2 373 4.2.6.8.1L2.|de 垂章垂音4垂4章面,音44垂·垂 373 4.2.6.8.2 2. TransmitWake 垂4垂 374 4.2.6.9 Disabled...1374 4.2.6.10 Loopback ….75 4.2.6.10. 1 Loopback Entry.. 4.2.6.10.2 LoopbackActive... 378 4.2.6.10.3 Loopback Exit 音垂垂面垂4,4垂垂,音垂 379 4.2.6.11 Hot Reset.………………… 380 4.2.7 Clock Tolerance Compensation 381 4.2.7.1 SKP Ordered Set for 8b/10b Encoding …382 4. 2.7.2 SKP Ordered Set for 128b/130b Encoding..... ∴382 4.2.7.3 Rules for transmitters 386 4.2.7.4 Rules for receivers 387 4.28 Compliance Pattern in8b/10 b Encoding…… 4.2.9 Modified Compliance Pattern in 8b/10b Encoding 389 4.2.10 Compliance Pattern in 128b/130b Encoding 390 4.2.11 Modified Compliance Pattern in 128b/130b Encoding 393 4.2.12 Jitter Measurement Pattern in 128b/130b. 393 4.2.13 Lane Margining at Receiver 着 394 4.2.13.1 Receiver Number, Margin Type, Usage ModeL, and margin Payload Fields 394 Page 7 5.0-1.0-PUB-PCI Express Base Specification Revision 5.0 Version 1.0 4. 13.1.1 Step Margin Execution Status... 音垂音 4. 13.1.2 Margin Payload for Step Margin Commands 399 4.2.13.2 Margin command and response flow 翻音 400 4.2.13.3 Receiver Margin Testing Requirements…………,…….….….….……….……….….403 4.3 Reimers 407 4.3.1 Retimer Requirements 4.3.2 Supported Retimer Topologies 409 4.3.3 Variables 4.3.4 Receiver Impedance Propagation Rules........411 4.3.5 Switching Between Modes.... 411 4.3.6 Forwarding Rules.. …411 4.3.6.1 Forwarding type rules. 2412 4.3.6.2 Orientation and lane numbers rules 2412 4.3.6.3 Electrical ldle exit rules wwwwwwwwwwwwwww 413 4.3.6.4 Data Rate Change and determination Rules.............................415 4. 3.6.5 Electrical ldle Entry rules 416 4.3.6.6 Transmitter Settings Determination Rules.. 417 4,3.6.7 Ordered set modification rules mw.wmwwwwmwmwwwwww 418 4.3.6. 8 DLLP, TLP, and Logical ldle Modification Rules..... 420 4.3.6. 9 8b /10b Encoding Rules..... 421 43.6.108b/10 b Scrambling rules….................,..,.21 4.3.6.11 Hot reset rules…… 421 43.6. 12 Disable link rules …9421 4.3.6.13 Loopback…...….…..…..….….….22 4.3.6. 14 Compliance Receive Rules ........423 4.3.6.15 Enter Compliance rules.,.,.,,.,.,.,.,.,.,.,,.,,,.,.,.…,,,….…...24 3.7 Execution Mode rules 427 4.3.7.1 CompLoad Board Rules ,427 4.3.7.1.1 CompLoad Board Entry ...............427 4.3.7.1.2 CompLoadBoard Pattern 427 4.3. 7.1.3 CompLoad Board Exit 428 43.7.2 Link Equalization Rules…… 429 43.7.2.1 Downstream Lanes ,ww...o.,,,,,,,,,,,,,,,,, 429 4.3.7.2.1.1 Phase2.429 4.3. 7.2.1.2 Phase 3 Active 429 4.3.7.21.3 Phase 3 Passive. 4.3.7.2.2 Upstream Lanes…,…, 音垂垂面垂4,4垂垂,音垂 430 4.3.7.2.2.1 Phase2 Active,,……………………… 430 4.3.7.2.2.2 Phase 2 Passive ………………430 4.3.7.2.2.3 Phase3 430 4.3.7.2.3 Force Timeout 垂垂44垂·重 431 4.3.7. 3 Slave Loopback. 431 4.3.7.3. 1 Slave Loopback Entry........ 431 4.3.7.3.2 Slave Loopback. Active..... ,432 4.3.7.3.3 Slave Loopback Exit 432 4.3.8 Retimer Latency……,…,…, 432 438.1 Measurement ∴432 4.3.8.2 Maximum Limit on Retimer Latency 432 4.3.8. 3 Impacts on Upstream and downstream Ports............ 433 4.3.9SR|S P 5.0-1.0-PUB-PCI Express Base Specification Revision 5.0 Version 1.0 4.3.10 L1 PM Substates Support 音垂音 4.3. 11 Retimer Configuration Parameters 436 43, 11.1 Global parameters 翻音 437 4.3. 11.2 Per Physical Pseudo port Parameters 437 4.3.12 In Band Register Access Power Management… 439 5.1 Overview ……439 5.2 Link State Power management 40 5.3 PCl-PM Software Compatible Mechanisms 444 5.3. 1 Device Power Management States(D-States)of a Function 444 5.3.1.1 Do State 445 5.3.1.2D1 State…,, ……………………………445 5.3.13 D2 State 445 5.3.1.4 D3 State …,1446 5.3.1.4.1 D3Hot state 447 5.3. 1.4.2 D3 Cold State 448 5.3.2 PM Software Control of the Link Power Management State 449 5.3.2.1 Entry into the Ll State 450 5.3.2.2 Exit from L1 State 垂垂垂 453 5.3.2.3 Entry into the L2/L3 Ready State 454 5.3.3 Power Management Event Mechanisms... 454 5.3.3.1 Motivation 454 53.32 Link Wakeup… 455 5.3.3.2. 1 PME Synchronization …456 5.3.3.3 PM_PME Messages. 458 5.3.3.3.1 PM PME"Backpressure " Deadlock Avoidance 45 5.3.3.4 PME Rules 4. 5.3.3.5 PM PME Delivery State Machine 5.4 Native PCI Express Power Management Mechanisms . 5.4.1 Active State Power Management(ASPM) 460 5.4.1.1 LOs ASPM State 462 5.4.1.1.1 Entry into the Los state 463 5.4.1.1.2 Exit from the los state 464 5.41.2L1 ASPM State 464 5.4.1.2. 1 ASPM Entry into the Ll State 465 5.4.1.2.2 Exit from the l1 state 471 5413 ASPM Configuration……… 474 5.4.1.3.1 Software Flow for Enabling or Disabling ASPM 477 5L1PMSubstates.wwwwwwwwww....,478 5.5.1 Entry conditions for Ll PM Substates and L1.0 Requirements 482 5.5.2 Ll1 Requirements 483 55.21 Exit from l11…… 483 5.5.3 L1.2 Requirements 484 5.5.3.1L1.2. Entry….....…..…. 485 55.32L1.2.|de 486 5.5.3.3L1.2Exit 486 5.5.3. 3.1 Exit from L1. 2 487 5.5.4 L1 PM Substates Configuration 5.5.5 L1 PM Substates Timing Parameters 488 Page 9 5.0-1.0-PUB-PCI Express Base Specification Revision 5.0 Version 1.0 5.5.6 Link Activation 音垂音 5.6 Auxiliary Power Support.......,,,…,………,490 5.7 Power Management System Messages and DLLPs 490 5.8 PCl Function power state transitions.mww..w.w...m., 491 5. 9 State Transition Recovery Time Requirements 音,4音面音音音音面垂垂音看音是垂看垂面音套音垂垂面面看音着音垂面·面垂垂 492 5.10 PCI Bridges and Power Management…… ∴493 5.10.1 Switches and PCI Express to PCI Bridges 494 5. 11 Power Management Events ,494 6. System Architecture 495 61 Interrupt and Pme Support……… 495 6.1.1 Rationale for PCi Express Interrupt model …495 6.1.2 PCl-compatible INTx Emulation ......495 6.1.3 IN TX Emulation Software model 垂B 496 6.1.4 MSI and MSl-X Operation 496 6.1.4.1 MSI Configuration 497 6. 1.4.2 MSI-X Configuration 6.1.4.3 Enabling Operati 499 6.1.4.4 Sending messages...... 500 6. 1.4.5 Per-vector Masking and Function Masking 2500 6. 1.4.6 Hardware/ Software Synchronization 6.1.4.7 Message Transaction Reception and Ordering Requirement -. 501 503 6.1.5 PME Support.… 6.1.6 Native PME Software Model .503 6.1.7 Legacy PME Software Model ..... 504 6.1.8 Operating System Power Management Notification.. 504 6.1.9 PME Routing Between PCI Express and 6.2 Error Signaling and Logging 6.2.1 Scope 505 6.2.2 Error Classification 505 6.2.2.1 Correctable errors 506 6.2.2.2 Uncorrectable errors .507 6.2.2.2.1 Fatal Errors ,4 .......507 6.2.2.2.2 Non-Fatal Errors 507 62.3 Error Signaling…… 507 6.2.3.1 Completion Status 507 6.2.3.2 Error Messages …507 6.2.3.2.1 Uncorrectable Error Severity Programming(Advanced Error Reporting 6.2.3.2.2 Masking Individual Errors. 6.2.3.23 Error pollution 509 6.2.3.2. 4 Advisory Non-Fatal Error Cases 510 6.2.3.2.4.1 Completer Sending a Completion with UR/CA Status 510 6.2.3.2. 4.2 Intermediate Receiver ∴511 6.2.3.2.4.3 Ultimate PCI Express Receiver of a Poisoned TLP 511 623244 Requester with Completion Timeout……… 512 6.2.3.2.4.5 Receiver of an Unexpected Completion 512 6.2.3.2.5 Requester Receiving a Completion with UR/CA Status 512 6.2.3.3 Error Forwarding(Data Poisoning 512 6.2.3.4 Optional Error Checking..........513 6.2.4 Error Logging… 513 P OT a8e