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基于单片机的温度控制系统外文翻译(完整资料).doc
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基于单片机的温度控制系统外文翻译(完整资料).doc
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基于单片机的温度控制系统外
文翻译(完整资料)
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外文原文:
De s i g n o f th e Temp e r at u r e Control Sy s t e m B
ased on AT89C51
ABSTRACT
The principle and functions of the temperature control system bas
ed on micro controller AT89C51 are studied, and the tempera
ture measurement unit consists of the 1—Wire bus digital temperatur
e sensor DS18B20。 The system can be expected to detect the preset
temperature, display time and save monitoring data。
An alarm will be given by system if the temperature exceeds the u
pper and lower limit value of the temperature which can be set di
scretionarily and then automatic control is achieved, thus t
he temperature is achieved monitoring intelligently within a certain r
a n g e. B asing o n p r i nci p l e o f t h e system, it is easy to m a
ke a variety o f ot h e r no n —li n ear contro l s y stems so lo n g a s
the software design is reasonably changed. The system has been proved to
be accurate, reliable and satisfied through field practice.
KEYWORDS: AT89C51; micro controller; DS18B20; tem
perature 1 INTRODUCTION
Temper at u re is a very im p ortan t par amet e r in human li f
e. In the modern society, temperature control (TC) is not only u
sed in industr ial pro duction, but also widely used in other f
ields. With the improvement of the life quality, we can find the TC a
ppliance in hotels, factories and home as well. And the trend that T
C will better serve the whole society, so it is of great signific
ance to measure and control the temperature. Based on the AT89
C51 and temperature sensor DS18B20, this system controls the condi
tion temperature intelligently。 The temperature can be set discretio
narily within a certain range。 The system can show the time on LC
D, and save monitoring data; and automatically control
the temperature when the condition temperature exceeds the upper
and lower lim it value . By d oi ng so it is to kee p the tem pe ra
ture unchanged. The system is of high anti-jamming, high control p
recision and flexible design; it also fits the rugged environment。 I
t is mainly used in people's life to improve the quality of the w
ork and life。 It is also versatile, so that it can be convenient to ext
end the use of the system。 So the design is of profound importance. Th
e general design, hardware design and software design of the sy
stem are covered。
1.1 Introduction
The 8—bit AT89C51 CHMOS microcontrollers are designed to hand
le high-spee d calc u lations a n d fa st inp u t/ o utpu t o p e rat i ons. M
CS 51 microcontrollers are typically used for high-speed event c
o ntrol sy s tem s 。 C o m mercial a pp l icati o n s incl u de mo d em s ,
motor—control systems, printers, photocopiers, air conditione
r c o ntro l s y st em s, d isk d ri ve s, and m e dic a l instr umen t
s. The a u t o mo t i ve in d ustry us e MCS 51 m i cr o co n tro l l e rs
in engine-con t rol s yste m s, ai r b a g s , s u spen s i o n sys t em s ,
and antilo c k braki n g s y st e m s ( A B S) 。 The AT89 C 5 1 is e sp e ci a
lly well suited to applications that benefit fr om its pr oces si ng sp eed
and e n h a n ced on—chip p e r ipheral fun c t i o n s set, such as automot i
ve power-train control, vehicle dynamic suspension, antilock brak
i n g , a n d s t abi l i t y c ont r ol appli c a ti o ns 。 Because o f t h
ese critical applications, the market requires a reliable cost-effective
controller with a low interrupt latency response, ability to se
rvice the high number of time and event driven integrated peripher
als needed i n real ti m e ap p l i ca t io n s , a n d a
CPU with above average processing power in a single package。 The fin
ancial and legal risk of having devices that operate unpredictabl
y is very high. Once in the market, particularly in mission critical
applications such as an autopilot or anti-lock braking system,
mistakes are financially prohibitive。 Redesign costs can run as
high as a $500K, much more if the fix means 2 back annotating it acro
ss a product family that share the same core and/or periphera
l design flaw。 In addition, field replacements of components is e
xtremely expensive, as the devices are typically sealed in modules wi
th a total value several times that of the component。 To mitigat
e these problems, it is essential that comprehensive testing of the
controllers be carried out at both the component level and s
ystem level under worst case environmental and voltage condition
s. This complete and thorough validation necessitates not only a
well—defined process but also a proper environment and tools
to faci l itate a nd exec ute t he m issio n s uc c es s fully. Intel Chandl e
r Platform Engineering group provides post silicon system validation
(SV) of various micro-controllers and processors. The system vali
dation process can be broken into three major parts. The type of t
he device and its application requirements determine whic
h types of testing are performed on the device.
1.2 The AT89C51 provides the following standard features
4Kbytes o f F l a s h , 1 2 8 b y t e s o f R A M, 32 I/O lines , t w
o 16—bittimer/counters, a five vector two-level interrupt archi
tecture, a full duple ser—ial port, on-chip oscillator and
clock circuitry。 In addition, the AT89C51 is designed with sta
tic logic for operation down to zero frequency and supports
two software selectable power saving modes。 The Idle
Mode stops the CPU while allowing the RAM, timer/counters, se
rial port and interrupt sys —tem to continue functioning。
The Power—down Mode savesthe RAM contents but freezes the oscil
–lator disabling all other chip functions until the next hardware rese
t.
1.3Pin Description
VCC Supply voltage。
GND Ground。
Port 0:Port 0 is an 8-bit open—drain bi-directional I/O port。 As a
n output port, each pin can sink eight TTL inputs. When 1s are w
ritten to port 0 pins, the pins can be used as high impedance inp
uts. Port 0 may also be configured to be the multiplexed low order a
ddress/data bus during accesses to external program and dat
a memory. In this mode P0 has internal pull ups。 Port 0 also receiv
es the code bytes during Flash programming, and outputs th
e code bytes during program verification. External pull ups are r
equired during program verification.
Port 1:Port 1 is an 8-bit bi—directional I/O port with internal
pull ups。 The Port 1 output buffers can sink/so -urce four TTL input
s 。 Whe n 1 s ar e w r i t t e n to P o r t 1 pins t h ey a r e
pulled high by the internal pull ups and can be used as inputs。 As input
s, Port 1 pins that are externally being pulled low will source cur
rent (IIL) because of the internal pullups. Port 1 also receives
t he low—order a ddr e ss b ytes d u rin g Flash pro g ram m i n g and v
erification。
Port 2:Port 2 is an 8—bit bi-directional I/O port with interna
l pull ups。 The Port 2 output buffers can sink/source four TT
L inputs. When 1s are written to Port 2 p in s t hey ar e pulled hi g
h by the internal pull ups and can be used as inputs. As inputs, Por
t 2 pins that are externally being pulled low will source curren
t (IIL) because of the internal pull ups. Port 2 emits the high-orde
r address byte during fetches from external program memory an
d during accesses to Port 2 pins that are externally being pul
led low will source current (IIL) because of the internal pull up
s。 Port 2 emits the high—order address byte during fetches fro
m external program memory and during accesses to external data me
mory that use 16-bit addresses (MOVX@DPTR)。 In this application,
it uses st r ong inter n al pull—up s w h e n em i tt in g 1s. D ur i ng ac c
esses to external data memory that use 8—bit addresses (MOVX @ RI),
Port 2 emits the contents of the P2 Special Function Register。 Por
t 2 also receives the high—order
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