基于单片机的高速数据采集系统设计说明.doc
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目 录
1.绪论..........................................................................................................................................................................1
1.1 课题研究的意义.......................................................................................................................................1
1.2 数据采集技术的发展历程和现状...........................................................................................................1
1.3 本文的研究容...........................................................................................................................................2
1.4 系统设计涉与的理论分析.......................................................................................................................2
2.系统设计.................................................................................................................................................................5
2.1 方案选择.......................................................................................................................................................5
2.2 系统框图.......................................................................................................................................................6
3.单元电路设计.........................................................................................................................................................6
3.1 信号调理电路..............................................................................................................................................6
3.2 高速Ａ／Ｄ模块..........................................................................................................................................8
3.3 FPGA 模块设计...........................................................................................................................................8
3.4MCU 模块设计.............................................................................................................................................9
3.5 数据采集通道总体原理图..........................................................................................................................9
3.6 硬件电路总体设计....................................................................................................................................10
4.软件设计...............................................................................................................................................................10
4.1 信号采集与存储控制电路工作原理........................................................................................................10
4.2 信号采集与存储控制电路的 FPGA 实现................................................................................................11
4.3 原理图中的各底层模块采用 VHDL 语言编写.......................................................................................12
4.3.1 三态缓冲器模块 TS8......................................................................................................................12
4.3.2 分频器模块 fredivid........................................................................................................................13
4.3.3 地址锁存器模块 dlatch8.................................................................................................................14
4.3.4 地址计数器模块 addrcount............................................................................................................15
4.3.5 双口 RAM 模块 lpm_ram_dp.........................................................................................................16
4.4 数据显示模块设计....................................................................................................................................18
4.4.1 主程序.............................................................................................................................................18
4.4.2 INT0 中断服务程序........................................................................................................................19
4.4.3 INT1 中断服务程序........................................................................................................................19
4.5 软件仿真.....................................................................................................................................................20
4.5.1 三态缓冲器模块 TS8......................................................................................................................20
4.5.2 分频器模块 fredivid........................................................................................................................20
4.5.3 地址锁存器模块 dlatch8.................................................................................................................21
4.5.4 地址计数器模块 addrcount............................................................................................................21
5.系统调试...............................................................................................................................................................21
5.1 单片机子系统调试....................................................................................................................................22
5.2 FPGA 子系统调试.....................................................................................................................................22
5.3 高速 A/D 模块的调试................................................................................................................................22
6 总结........................................................................................................................................................................22
致...............................................................................................................................................................................22
参考文献..................................................................................................................................................................23
附录...........................................................................................................................................................................25
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