An Approximate Versatile Video Coding
Fractional Interpolation Hardware
Hasan Azgin, Ercan Kalali, Ilker Hamzaoglu
Faculty of Engineering and Natural Sciences, Sabanci University
34956 Tuzla, Istanbul, Turkey
{hasanazgin, ercankalali, hamzaoglu}@sabanciuniv.edu
Abstract— In this paper, approximate Versatile Video Coding
(VVC) fractional interpolation filters are proposed. They
significantly reduce computational complexity of VVC fractional
interpolation with a negligible PSNR loss and bit rate increase. In
this paper, an approximate VVC fractional interpolation
hardware implementing the proposed approximate filters is
designed and implemented. The proposed approximate hardware
has less area and up to 40% less power consumption than exact
VVC fractional interpolation hardware. Therefore, it can be used
in consumer electronics products that require low power VVC
encoder hardware.
Keywords—VVC, Fractional Interpolation, Approximate
Computing, Hardware Implementation, Low Power.
I. I
NTRODUCTION
ITU and ISO are developing a new international video
compression standard called Versatile Video Coding (VVC)
[1]-[6]. VVC will have higher compression efficiency than
High Efficiency Video Coding (HEVC) standard at the expense
of much higher computational complexity [7]-[11].
HEVC standard uses 3 different 8-tap FIR filters for
fractional interpolation (FI). It interpolates 3 horizontal and 3
vertical half pixels and 9 quarter pixels for each integer pixel.
However, VVC standard uses 15 different 8-tap FIR filters for
fractional interpolation. It interpolates 15 horizontal and 15
vertical half pixels and 225 quarter pixels for each integer
pixel. Therefore, VVC fractional interpolation has much higher
computational complexity than HEVC fractional interpolation.
In this paper, approximate VVC fractional interpolation
filters are proposed. The proposed approximate filters consist
of 14 different 3-tap FIR filters and 1 4-tap FIR filter. The
proposed approximate filters significantly reduce the
computational complexity of VVC fractional interpolation with
a negligible PSNR loss and bit rate increase.
In this paper, an approximate VVC fractional interpolation
hardware implementing the proposed approximate fractional
interpolation filters is designed and implemented using Verilog
HDL. The proposed approximate hardware implements
multiplication operations using add and shift operations. It can
process 47 full HD (1920x1080) video frames per second (fps).
It has less area and up to 40% less power consumption than
exact VVC fractional interpolation hardware.
Approximate HEVC fractional interpolation filters are
proposed in [12]. There is no approximate VVC fractional
interpolation filter in the literature.
An exact VVC fractional interpolation hardware is proposed
in [13]. However, this hardware can only be used for motion
compensation. The hardware proposed in this paper can be
used for both motion estimation and motion compensation.
While the hardware in [13] calculates one fractional pixel for
each integer pixel, the hardware proposed in this paper
calculates 255 fractional pixels for each integer pixel.
The exact original VVC fractional interpolation hardware
proposed in [14] implements 15 fractional interpolation filters
in parallel. The proposed approximate VVC fractional
interpolation hardware has less area and up to 40% less power
consumption than this hardware.
There are several HEVC fractional interpolation hardware
implementations in the literature [15]-[17]. Since VVC
fractional interpolation has much higher computational
complexity than HEVC fractional interpolation, the proposed
VVC fractional interpolation hardware has larger area and
lower performance than them.
The rest of the paper is organized as follows. Section II
explains the VVC fractional interpolation algorithm. The
proposed approximate VVC fractional interpolation filters are
explained in Section III. Section IV presents the proposed
approximate VVC fractional interpolation hardware and gives
its implementation results. Section V presents the conclusions.
II. VVC
F
RACTIONAL
I
NTERPOLATION
A
LGORITHM
VVC standard uses 15 different 8-tap FIR filters for
fractional interpolation. The coefficients of these 15 FIR filters
are shown in Table I. A
-3
– A
4
show input pixels for a filter
where sub-indices represent the indices of coefficients. The
8-tap FIR filter equation is shown in (1) as an example.
ܨ
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െܣ
ିଷ
Ͷכܣ
ିଶ
െͳͳכܣ
ିଵ
Ͷͷכܣ
͵Ͷ כ ܣ
ଵ
െͳͲכܣ
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ب
(1)
Integer pixels and fractional pixels are shown in Fig. 1.
There are 15 horizontal half pixels between two neighboring
horizontal integer pixels and 15 vertical half pixels between
two neighboring vertical integer pixels. These half pixels are
interpolated from nearest integer pixels by using 15 different
FIR filters. There are 225 quarter pixels between horizontal
and vertical half pixels, as shown in Fig. 1. These quarter
pixels are interpolated from nearest horizontal half pixels
using 15 different FIR filters.
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