L6: 6.111 Spring 2004 4Introductory Digital Systems Laboratory
Handling
Handling
Metastability
Metastability
Preventing metastability turns out to be an impossible problem
High gain of digital devices makes it likely that metastable conditions will
resolve themselves quickly
Solution to metastability: allow time for signals to stabilize
How many registers are necessary?
Depends on many design parameters(clock speed, device speeds, …)
In 6.111, one or maybe two synchronization registers is sufficient
DQ
Complicated
Sequential Logic
System
Clock
DQ
DQ
Likeley to be
metastable
right after
sampling
Very unlikely to
be metastable for
>1 clock cycle
Extremely unlikely
to be metastable for
>2 clock cycle
