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Important: FA626TE55EE0001HD0AG (2.1.0) is currently retained by Faraday. Please contact
Faraday local service team for further information.
FA626TE|FA626TE55EE0001HC0HA
FA626TE54EE0001HC0HA|FA626TE55EE0001HD0AG
32-BIT RISC PROCESSOR
Data Sheet
Rev.: 2.17
Issue Date: January 2011
REVISION HISTORY
FA626TE|FA626TE55EE0001HC0HA|FA626TE54EE0001HC0HA|FA626TE55EE0001HD0AG
Data Sheet
Date Rev. From To
Jul. 2007 1.0 - Original
Oct. 2007 1.1 - Added a new IP: FA626TE55EE0001HD0AG
Dec. 2007 1.2 - Updated the IP version
Feb. 2008 1.3 - Updated the content due to ECO
Feb. 2008 1.4 - Updated the IP version
Mar. 2008 1.5 - Updated the IP version
Apr. 2008 1.6 - Added a new IP: FA626TE54EE0001HC0HA
May 2008 1.7 - z Modified the power-down control in Section 9.3
z Modified the contents in Table 2-8
May 2008 1.8 - Added a new IP: FA626TE
Jun. 2008 1.9 - z Modified the cp15 registers 1-0 and 1-1
z Added Bit 14 and Bit 16 on page 14
Jun. 2008 2.0 Updated the IP version of FA626TE55EE0001HC0HA from
(1.0.0) to (1.1.0)
Aug. 2008 2.1 - Updated the IP version of FA626TE55EE0001HD0AG from
(0.2.0) to (0.3.0)
Aug. 2008 2.2 - Updated the IP version of FA626TE55EE0001HD0AG from
(0.3.0) to (1.0.0)
Oct. 2008 2.3 - Modified the scratch pad size in Section 1.7 and Section 8.1
Jan. 2009 2.4 - Updated the IP versions:
z FA626TE55EE0001HC0HA from (1.1.0) to (2.0.0)
z FA626TE from (0.0.1) to (0.1.0)
Aug. 2009 2.5 - Updated the IP versions:
z FA626TE55EE0001HD0AG from (1.0.0) to (1.1.0)
z FA626TE from (0.1.0) to (1.2.0)
Sept. 2009 2.6 - Revised the pin descriptions
Dec. 2009 2.7 - Updated the IP version of FA626TE to (1.3.0)
Jan. 2010 2.8 - Updated the IP version of FA626TE55EE0001HD0AG to
(1.1.1)
Feb. 2010 2.9 - Added test pin signal descriptions in Table 11-7 and
Table 11-9
Date Rev. From To
Mar. 2010 2.10
- Updated the IP version of FA626TE55EE0001HD0AG to
(1.2.0)
May 2010 2.11 - Updated the descriptions of the Scratchpad Interface Signals
in Table 11-5
Jun. 2010 2.12 - Updated the IP version of FA626TE55EE0001HD0AG to
(2.0.0)
Jul. 2010 2.13 - Updated the IP version of FA626TE to (1.3.1)
Aug. 2010 2.14 - Updated the IP version of FA626TE55EE0001HC0HA from
(2.0.0) to (2.1.0)
Aug. 2010 2.15 - Updated the IP version of FA626TE55EE0001HD0AG to
(2.1.0)
Nov. 2010 2.16 - Updated the IP version of FA626TE to (1.3.2)
Jan. 2011 2.17 - Added the AXI DMA specifications
© Copyright Faraday Technology, 2011
All Rights Reserved.
Printed in Taiwan 2011
Faraday and the Faraday Logo are trademarks of Faraday Technology Corporation in Taiwan and/or other countries.
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in
implantation or other life support application where malfunction may result in injury or death to persons. The information contained in this document
does not affect or change Faraday's product specification or warranties. Nothing in this document shall operate as an express or implied license or
indemnity under the intellectual property rights of Faraday or third parties. All information contained in this document was obtained in specific
environments, and is presented as an illustration. The results obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will Faraday be liable for damages
arising directly or indirectly from any use of the information contained in this document.
Faraday Technology Corporation
No. 5, Li-Hsin Road III, Hsinchu Science Park, Hsinchu City, Taiwan 300, R.O.C.
Faraday's home page can be found at:
http://www.faraday-tech.com
FA626TE|FA626TE55EE0001HC0HA|FA626TE54EE0001HC0HA|FA626TE55EE0001HD0AG Data Sheet
www.faraday-tech.com
i
TABLE OF CONTENTS
Chapter 1 Introduction............................................................................................................................ 1
1.1 Version of the IP......................................................................................................... 3
1.2 CPU Core ................................................................................................................... 3
1.3 Branch Prediction Unit (BPU)..................................................................................... 3
1.4 Instruction Cache (ICache)......................................................................................... 4
1.5 Data Cache (DCache) ................................................................................................ 4
1.6 Memory Management Unit (MMU)............................................................................. 4
1.7 IScratchpad and DScratchpad ................................................................................... 5
1.8 Bus Interface Unit (BIU) ............................................................................................. 5
1.9 Write Buffer (WB) ....................................................................................................... 5
1.10 ICE.............................................................................................................................. 6
1.11 Power-saving Control Unit.......................................................................................... 6
1.12 Coprocessor Transfer Instruction............................................................................... 6
Chapter 2 Programming Model.............................................................................................................. 7
2.1 General Description.................................................................................................... 8
2.2 CP15 Register Description......................................................................................... 8
2.2.1 CR0-0 Identification Code Register (ID)........................................................ 9
2.2.2 CR0-1 Cache Type Register (CTR) ............................................................ 11
2.2.3 CR0-3 TLB Type Register (TTR)................................................................. 13
2.2.4 CR1-0 Configuration Register (CFG) .......................................................... 14
2.2.5 CR1-1 Configuration Register (CFG) Auxiliary Control Register (AUX) ..... 18
2.2.6 CR2 Translation Table Base Register (TTB) ............................................... 19
2.2.7 CR3 Domain Access Control Register (DAC) ............................................. 19
2.2.8 CR5 Fault Status Register (FSR) ................................................................ 20
2.2.9 CR6 Fault Address Register (FAR) ............................................................. 21
2.2.10 CR7 Cache Operation Register (Write only) ............................................... 21
2.2.11 CR8 TLB Operation Register (Write only)................................................... 24
2.2.12 CR9_0 Data/Instruction Cache Lockdown Register (DCL/ICL) .................. 25
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