基于 VSC 的 UPFC（统一电力流控制器）.zip

% ==========UPFC control========= % % By: % % Abdul Wahab Korai @ University of Duisburg-Essen % % % % Date: 18/11/2015 % % ================================================================= % %% % Parameters file clc; clear all; %% Sample times Ts_PWM = 5e-6; Ts_Control = 50e-6; % Control systems sample Ts_Power = Ts_PWM; % Default value %% Grid parameters Fnom = 50; % Nominal system frequency (Hz) Vnom_grid = 500e3; % nominal voltage (L-L rms) Psc_grid = 20000e6; % Short-circuit level (VA) %% Shunt Converter parameters % DC link: Pnom_dc_3L = 200e6; % Nominal DC link Power (VA) Vnom_dc_3L = Vnom_grid/0.612; % Nominal DC link voltage (V) H_3L = 1/Fnom*2; % DC link stored energy constant(s) = 2 cycles Clink_3L = Pnom_dc_3L*H_3L*2 /Vnom_dc_3L^2; % DC link capacitor (F) Vc_Initial_3L = Vnom_dc_3L/2; % capacitor initial voltage (V) % Transformer: Pnom_3L = Pnom_dc_3L; % Transformer nominal power (VA) Vnom_prim_3L = Vnom_grid; % Nominal primary voltage (V) m_nom_3L = 0.8; % Nominal modulation index Vnom_sec_3L = 0.5*Vnom_dc_3L/sqrt(2)*sqrt(3)*m_nom_3L; % Nominal secondary voltage (V) % Control Parameters Fc_3L=33*Fnom; % PWM carrier frequency (Hz) Freq_Filter=1000; % Measurement filters natural frequency (Hz) Lact = 0.15*((Vnom_sec_3L/1000)*1e3)^2/(Pnom_3L)/314.159 % VDC controller Kp_VDCreg_3L= 3; % Proportional gain Ki_VDCreg_3L= 300; % Integral gain LimitU_VDCreg_3L= 1.5; % Output (Idref) Upper limit (pu) LimitL_VDCreg_3L= -1.5; % Output (Idref) Lower limit (pu) % Current controller Kp_Ireg_3L= 0.2/2; % Proportional gainKp_VDCreg_3L Ki_Ireg_3L= 15; % Integral gain LimitU_Ireg_3L= 1.5; % Output (Vdq_conv) Upper limit (pu) LimitL_Ireg_3L= -1.5; % Output (Vdq_conv) Lower limit (pu)