目录
1. 总体方案.............................................................1
2. 顶层逻辑电路图组成、信号定义及原理阐述...............................1
3. 底层功能模块设计.....................................................2
3.1 “秒”与“分”的计数器模块设计..................................2
3.2 “时”的计数器模块设计..........................................4
3.3 时钟模块的设计..................................................5
3.4 校“时”校“分”模块设计........................................7
3.5 时段控制模块设计................................................9
3.6 整点报时模块设计...............................................10
3.7 模块整合.......................................................12
4. 芯片型号、定义芯片管脚号及下载过程..................................13
4.1 芯片型号.......................................................13
4.2 定义芯片管脚号.................................................14
4.3 下载过程.......................................................15
5. 遇到的问题及解决方法................................................17
5.1 使用Block Design File时遇到编译报错............................17
5.2 使用Verilog HDL File时遇到编译报错.............................17
5.3 下载程序时遇到的问题...........................................17
6. 最终结论............................................................18
7. 项目的特点和实用性..................................................18
8. 结束语..............................................................18
9. 参考教材及文献......................................................18
