################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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Verilog 简易单周期CPU,包含指令存储器和数据存储器的ip核调用,控制器,寄存器堆,ALU,单周期CPU的实现。控制器包含13条指令,可扩展,包含一个测试用的小指令段,与RAM有关的指令暂未测试。可运行。
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Verilog 简易单周期CPU,包含指令存储器和数据存储器的ip核调用,控制器,寄存器堆,ALU,单周期CPU的实现 13条 (349个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
elaborate.bat 1KB
simulate.bat 938B
compile.bat 822B
runme.bat 229B
runme.bat 229B
xsim_1.c 13KB
ROM.coe 265B
ROM.coe 265B
ROM.coe 265B
ROM.coe 265B
ROM.coe 265B
ROM.coe 265B
ROM.coe 265B
ROM.coe 265B
ROM.coe 265B
ROM.coe 265B
ROM.coe 265B
xsim.dbg 96KB
data_RAM.dcp 38KB
data_RAM.dcp 37KB
data_RAM.dcp 37KB
data_RAM.dcp 37KB
inst_ROM.dcp 31KB
inst_ROM.dcp 31KB
inst_ROM.dcp 31KB
inst_ROM.dcp 31KB
ROM_D.dcp 21KB
ROM_D.dcp 21KB
ROM_D.dcp 21KB
compile.do 733B
compile.do 730B
compile.do 699B
compile.do 696B
compile.do 649B
compile.do 646B
compile.do 635B
compile.do 632B
simulate.do 331B
simulate.do 327B
simulate.do 325B
simulate.do 325B
simulate.do 318B
simulate.do 318B
elaborate.do 203B
elaborate.do 199B
simulate.do 193B
simulate.do 187B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
xsimk.exe 170KB
run.f 473B
run.f 470B
run.f 453B
run.f 450B
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 65B
xsim.ini 26KB
xsim.ini 26KB
xsim.ini 26KB
xsimSettings.ini 1KB
webtalk.jou 729B
webtalk_29608.backup.jou 729B
vivado.jou 655B
vivado.jou 634B
vivado.jou 597B
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
runme.log 32KB
runme.log 29KB
elaborate.log 1KB
xvlog.log 1KB
webtalk_29608.backup.log 1KB
webtalk.log 1KB
vivado.log 904B
summary.log 903B
summary.log 903B
summary.log 903B
summary.log 903B
summary.log 903B
summary.log 903B
summary.log 903B
summary.log 903B
summary.log 903B
summary.log 903B
simulate.log 363B
xsimkernel.log 311B
xsimcrash.log 0B
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