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PCIE转PCI
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1999 PCIBus Solutions
Data Manual
Printed in U.S.A., 12/99 SCPS051
PCI2250
PCI-to-PCI Bridge
Data Manual
Literature Number: SCPS051
December 1999
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
iii
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Related Documents 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Introduction to the PCI2250 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 PCI Commands 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Configuration Cycles 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Special Cycle Generation 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Secondary Clocks 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Bus Arbitration 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Primary Bus Arbitration 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 Internal Secondary Bus Arbitration 3–5. . . . . . . . . . . . . . . . . . . .
3.6.3 External Secondary Bus Arbitration 3–6. . . . . . . . . . . . . . . . . . .
3.7 Decode Options 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Extension Windows With Programmable Decoding 3–6. . . . . . . . . . . . . .
3.9 System Error Handling 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.1 Posted Write Parity Error 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2 Posted Write Timeout 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.3 Target Abort on Posted Writes 3–7. . . . . . . . . . . . . . . . . . . . . . . .
3.9.4 Master Abort on Posted Writes 3–7. . . . . . . . . . . . . . . . . . . . . . .
3.9.5 Master Delayed Write Timeout 3–7. . . . . . . . . . . . . . . . . . . . . . . .
3.9.6 Master Delayed Read Timeout 3–7. . . . . . . . . . . . . . . . . . . . . . .
3.9.7 Secondary SERR
3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Parity Handling and Parity Error Reporting 3–7. . . . . . . . . . . . . . . . . . . . . .
3.10.1 Address Parity Error 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.2 Data Parity Error 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Master and Target Abort Handling 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Discard Timer 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 Delayed Transactions 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 Multifunction Pins 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.1 Compact PCI Hot Swap Support 3–9. . . . . . . . . . . . . . . . . . . . . .
3.14.2 PCI Clock Run Feature 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15 PCI Power Management 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.1 Behavior in Low Power States 3–10. . . . . . . . . . . . . . . . . . . . . . . .
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