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TexasInstruments-TMS470R1A384PZ-T.pdf
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TexasInstruments-TMS470R1A384PZ-T.pdf
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1
FEATURES
TMS470R1A384
www.ti.com
......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
16/32-Bit RISC Flash Microcontroller
23
• High-Performance Static CMOS Technology – Two Serial Communication Interfaces
(SCIs)
• TMS470R1x 16/32-Bit RISC Core
( ARM7TDMI™) – 2
24
Selectable Baud Rates
– 24-MHz System Clock (48-MHz Pipeline) – Asynchronous/Isosynchronous Modes
– Independent 16/32-Bit Instruction Set – Two Standard CAN Controllers (SCC)
– Open Architecture With Third-Party Support – 16-Mailbox Capacity
– Built-In Debug Module – Fully Compliant With CAN Protocol,
Version 2.0B
• Integrated Memory
– Class II Serial Interface B (C2SIb)
– 384K-Byte Program Flash
– Normal 10.4 Kbps and 4X Mode
– Three Banks With 18 Contiguous
41.6 Kbps
Sectors
– Three Inter-Integrated Circuit (I2C) Modules
– 32K-Byte Static RAM (SRAM)
(See I2C Notes in TMS470R1A384 Silicon
• Operating Features
Errata, Literature Number SPNZ148 )
– Core Supply Voltage (V
CC
): 1.71 V to 2.05 V
– Multi-Master and Slave Interfaces
– I/O Supply Voltage (V
CCIO
): 3.0 V to 3.6 V
– Up to 400 Kbps (Fast Mode)
– Low-Power Modes: STANDBY and HALT
– 7- and 10-Bit Address Capability
– Extended Industrial Temperature Range
• High-End Timer (HET)
• 470+ System Module
– 12 Programmable I/O Channels:
– 32-Bit Address Space Decoding
– 12 High-Resolution Pins
– Bus Supervision for Memory/Peripherals
– High-Resolution Share Feature (XOR)
– Analog Watchdog (AWD) Timer
– High-End Timer RAM
– Enhanced Real-Time Interrupt (RTI)
– 64-Instruction Capacity
– Interrupt Expansion Module (IEM)
• External Clock Prescale (ECP) Module
– System Integrity and Failure Detection
– Programmable Low-Frequency External
• Direct Memory Access (DMA) Controller
Clock (CLK)
– 32 Control Packets and 16 Channels
• 12-Channel 10-Bit Multi-Buffered
• Zero-Pin Phase-Locked Loop (ZPLL)-Based
Analog-to-Digital Converter (MibADC)
Clock Module With Prescaler
– 32-Word FIFO Buffer
– Multiply-by-4 or -8 Internal ZPLL Option
– Single- or Continuous-Conversion Modes
– ZPLL Bypass Mode
– 1.55-µs Minimum Sample/Conversion Time
• Expansion Bus Module (EBM) (PGE Package)
– Calibration Mode and Self-Test Features
– Supports 8- and 16-Bit Expansion Bus
• 55 Dedicated General-Purpose I/O (GIO) Pins
Memory Interface Mappings
and 39 Additional Peripheral I/Os (PGE)
– 40 I/O Expansion Bus Pins
• 14 Dedicated General-Purpose I/O (GIO) Pins
• Ten Communication Interfaces:
and 39 Additional Peripheral I/Os (PZ)
– Two Serial Peripheral Interfaces (SPIs)
• Flexible Interrupt Handling
– 255 Programmable Baud Rates
• Eight External Interrupts
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005 – 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
HET[1]
HET[2]
V
CCIO
GIOE[6]
HET[4]
HET[3]
GIOE[5]
V
SS
GIOE[2]
SPI2SOMI
SPI2ENA
SPI2SIMO
GIOE[3]
SPI2SCS
HET[5]
GIOE[4]
GIOD[0]
GIOH[1]
SCI2RX
SCI1RX
GIOE[0]
GIOB[0]
SCI1TX
SCI1CLK
GIOE[1]
SCI2TX
V
SS
SCI2CLK
V
CC
CAN2SRX
CAN2STX
SPI2CLK
GIOD[1]
GIOH[4]
GIOH[3]
GIOH[2]
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
AD
REFHI
AD
REFLO
V
CCAD
V
SSAD
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
GIOC[4]
GIOC[3]
RST
V
SS
V
CC
TEST
GIOH[5]
GIOC[2]
GIOA[4]/INT[4]
GIOC[1]
V
SS
V
CC
V
CCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
GIOC[0]
GIOA[1]/INT[1]/ECLK
V
CCIO
V
SS
GIOH[0]
GIOG[7]
GIOA[0]/INT[0]
GIOG[6]
GIOG[5]
TRST
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
GIOF[7]
GIOF[6]
GIOA[5]/INT[5]
PLLDIS
GIOF[5]
I2C2SCL
I2C2SDA
GIOF[4]
V
CC
V
SS
GIOF[3]
GIOF[2]
I2C1SCL
I2C1SDA
V
CCIO
V
SS
CAN1STX
CAN1SRX
GIOF[1]
CLKOUT
GIOF[0]
GIOA[7]/INT[7]
GIOA[6]/INT[6]
GIOE[7]
TCK
TDO
TDI
HET[0]
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
1
2
3
4
5
6
7
8
9
SPI1SCS
SPI1ENA
GIOG[4]
SPI1CLK
SPI1SIMO
GIOG[3]
SPI1SOMI
GIOG[2]
HET[6]
10
11
12
13
14
15
16
17
18
19
20
21
GIOG[1]
HET[7]
HET[8]
V
CC
V
SS
HET[18]
TMS2
TMS
HET[20]
HET[22]
GIOG[0]
C2SILPN
22
23
24
25
26
27
28
29
30
31
32
33
C2SIRX
GIOD[5]
C2SITX
V
CCIO
V
SS
GIOD[4]
I2C3SCL
I2C3SDA
GIOD[3]
V
CC
OSCOUT
OSCIN
34
35
36
V
SS
GIOD[2]
AWD
TMS470R1A384
SPNS110E – AUGUST 2005 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
• On-Chip Scan-Base Emulation Logic, IEEE • 100-Pin Plastic Low-Profile Quad Flatpack
Standard 1149.1
(1)
(JTAG) Test-Access Port (PZ Suffix)
• 144-Pin Plastic Low-Profile Quad Flatpack
(1)
The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
(PGE Suffix)
Scan Architecture specification. Boundary scan is not
supported on this device.
TMS470R1A384 144-Pin PGE Package (Top View) (Without Expansion Bus)
2 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
HET[1]
HET[2]
V
CCIO
EBDATA[6]
HET[4]
HET[3]
EBDATA[5]
V
SS
EBDATA[2]
SPI2SOMI
SPI2ENA
SPI2SIMO
EBDATA[3]
SPI2SCS
HET[5]
EBDATA[4]
EBADDR[0]
EBADDR[23]/EBADDR[15]
SCI2RX
SCI1RX
EBDATA[0]
EBDMAREQ[0]
SCI1TX
SCI1CLK
EBDATA[1]
SCI2TX
V
SS
SCI2CLK
V
CC
CAN2SRX
CAN2STX
SPI2CLK
EBADDR[1]
EBADDR[26]/EBADDR[18]
EBADDR[25]/EBADDR[17]
EBADDR[24]/EBADDR[16]
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
AD
REFHI
AD
REFLO
V
CCAD
V
SSAD
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
EBCS[6]
EBCS[5]
RST
V
SS
V
CC
TEST
EBHOLD
EBWR[1]
GIOA[4]/INT[4]
EBWR[0]
V
SS
V
CC
V
CCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
EBOE
GIOA[1]/INT[1]/ECLK
V
CCIO
V
SS
EBADDR[22]/EBADDR[14]
EBADDR[21]/EBADDR[13]
GIOA[0]/INT[0]
EBADDR[20]/EBADDR[12]
EBADDR[19]/EBADDR[11]
TRST
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
EBADDR[13]/EBDATA[15]
EBADDR[12]/EBDATA[14]
GIOA[5]/INT[5]
PLLDIS
EBADDR[11]/EBDATA[13]
I2C2SCL
I2C2SDA
EBADDR[10]/EBDATA[12]
V
CC
V
SS
EBADDR[9]/EBDATA[11]
EBADDR[8]/EBDATA[10]
I2C1SCL
I2C1SDA
V
CCIO
V
SS
CAN1STX
CAN1SRX
EBADDR[7]/EBDATA[9]
CLKOUT
EBADDR[6]/EBDATA[8]
GIOA[7]/INT[7]
GIOA[6]/INT[6]
EBDATA[7]
TCK
TDO
TDI
HET[0]
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
1
2
3
4
5
6
7
8
9
SPI1SCS
SPI1ENA
EBADDR[18]/EBADDR[10]
SPI1CLK
SPI1SIMO
EBADDR[17]/EBADDR[9]
SPI1SOMI
EBADDR[16]/EBADDR[8]
HET[6]
10
11
12
13
14
15
16
17
18
19
20
21
EBADDR[15]/EBADDR[7]
HET[7]
HET[8]
V
CC
V
SS
HET[18]
TMS2
TMS
HET[20]
HET[22]
EBADDR[14]/EBADDR[6]
C2SILPN
22
23
24
25
26
27
28
29
30
31
32
33
C2SIRX
EBADDR[5]
C2SITX
V
CCIO
V
SS
EBADDR[4]
I2C3SCL
I2C3SDA
EBADDR[3]
V
CC
OSCOUT
OSCIN
34
35
36
V
SS
EBADDR[2]
AWD
TMS470R1A384
www.ti.com
......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
TMS470R1A384 144-Pin PGE Package (Top View) (with Expansion Bus)
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TMS470R1A384
1
2
3
4
5
6
7
8
9
10
11
12
14
13
15
16
20
17
18
19
22
21
23
25
24
75
74
73
72
71
70
68
69
67
66
64
65
62
63
61
60
56
58
59
57
54
55
53
51
52
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AD
REFHI
AD
REFLO
V
CCAD
V
SSAD
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
RST
TEST
GIOH[5]
GIOA[4]/INT[4]
V
SS
V
CC
V
CCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
GIOA[1]/INT[1]/ECLK
V
CCIO
V
SS
GIOA[0]/INT[0]
TRST
HET[1]
HET[2]
V
CCIO
V
SS
HET[3]
HET[4]
HET[5]
SPI2SCS
SPI2ENA
SPI2SIMO
SPI2SOMI
SPI2CLK
CAN2STX
CAN2SRX
SCI2CLK
SCI2RX
SCI2TX
SCI1CLK
SCI1RX
SCI1TX
GIOB[0]
GIOH[1]
GIOH[2]
GIOH[3]
GIOH[4]
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
GIOA[5]/INT[5]
PLLDIS
I2C2SCL
I2C2SDA
V
CC
V
SS
I2C1SCL
I2C1SDA
CAN1STX
CAN1SRX
CLKOUT
GIOA[7]/INT[7]
GIOA[6]/INT[6]
TCK
TDO
TDI
HET[0]
SPI1SCS
SPI1ENA
SPI1CLK
SPI1SIMO
SPI1SOMI
HET[6]
HET[7]
HET[8]
HET[18]
TMS2
TMS
HET[20]
HET[22]
C2SILPN
C2SIRX
C2SITX
V
CCIO
V
SS
I2CSCL
I2C3SDA
V
CC
OSCOUT
OSCIN
V
SS
AWD
TMS470R1A384
SPNS110E – AUGUST 2005 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
TMS470R1A384 100-Pin PZ Package (Top View)
4 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
DESCRIPTION
TMS470R1A384
www.ti.com
......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
The TMS470R1A384
(1)
devices are members of the Texas Instruments TMS470R1x family of general-purpose
16/32-bit reduced instruction set computer (RISC) microcontrollers. The A384 microcontroller offers high
performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a
high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views
memory as a linear collection of bytes numbered upwards from zero. The A384 utilizes the big-endian format
where the most significant byte of a word is stored at the lowest-numbered byte and the least significant byte at
the highest-numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining low
costs. The A384 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The A384 devices contain the following:
• ARM7TDMI 16/32-bit RISC CPU
• TMS470R1x system module (SYS) with 470+ enhancements
• 384K-byte flash
• 32K-byte SRAM
• Zero-pin phase-locked loop (ZPLL) clock module
• Analog watchdog (AWD) timer
• Enhanced real-time interrupt (RTI) module
• Interrupt expansion module (IEM)
• Two serial peripheral interface (SPI) modules
• Two serial communications interface (SCI) modules
• Two standard CAN controllers (SCC)
• Three inter-integrated circuit (I2C) modules
• Class II serial interface B (C2SIb) module
• 10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
• High-end timer (HET) controlling 12 I/Os
• External clock prescale (ECP)
• Expansion bus module (EBM)
• Up to 87 I/O pins and 1 input-only pin (PGE suffix only), up to 51 I/O pins and 1 input-only pin (PZ suffix only)
The functions performed by the 470+ system module (SYS) include:
• Address decoding
• Memory protection
• Memory and peripherals bus supervision
• Reset and abort exception management
• Prioritization for all internal interrupt sources
• Device clock control
• Parallel signature analysis (PSA)
The enhanced real-time interrupt (RTI) module on the A384 has the option to be driven by the oscillator clock.
This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt
priority, and a device memory map. For a more detailed functional description of the SYS module, see the
TMS470R1x System Module Reference Guide (literature number SPNU189).
The A384 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz. When
in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. For more detailed
information on the flash, see the Flash section of this data sheet and the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
(1) Throughout the remainder of this document, the TMS470R1A384 is referred to as either the full device name or as A384.
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TMS470R1A384
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