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Data sheet acquired from Harris Semiconductor

SCHS222C

Features

• Independent Asynchronous Inputs and Outputs

• Expandable in Either Direction

• Reset Capability

• Status Indicators on Inputs and Outputs

• Three-State Outputs

• Shift-Out Independent of Three-State Control

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Applications

• Bit-Rate Smoothing

• CPU/Terminal Buffering

• Data Communications

• Peripheral Buffering

• Line Printer Input Buffers

• Auto-Dialers

• CRT Buffer Memories

• Radar Data Acquisition

Description

The ’HC40105 and ’HCT40105 are high-speed silicon-gate

CMOS devices that are compatible, except for “shift-out”

circuitry, with the CD40105B. They are low-power ﬁrst-in-out

(FIFO) “elastic” storage registers that can store 16 four-bit

words. The 40105 is capable of handling input and output

data at different shifting rates. This feature makes it

particularly useful as a buffer between asynchronous

systems.

Each work position in the register is clocked by a control ﬂip-

ﬂop, which stores a marker bit. A “1” signiﬁes that the posi-

tion’s data is ﬁlled and a “0” denotes a vacancy in that posi-

tion. The control ﬂip-ﬂop detects the state of the preceding

ﬂip-ﬂop and communicates its own status to the succeeding

ﬂip-ﬂop. When a control ﬂip-ﬂop is in the “0” state and sees a

“1” in the preceeding ﬂip-ﬂop, it generates a clock pulse that

transfers data from the preceding four data latches into its

own four data latches and resets the preceding ﬂip-ﬂop to

“0”. The ﬁrst and last control ﬂip-ﬂops have buffered outputs.

Since all empty locations “bubble” automatically to the input

end, and all valid data ripple through to the output end, the

status of the ﬁrst control ﬂip-ﬂop (DATA-IN READY) indicates

if the FIFO is full, and the status of the last ﬂip-ﬂop (DATA-

OUT READY) indicates if the FIFO contains data. As the

earliest data are removed from the bottom of the data stack

(the output end), all data entered later will automatically

propagate (ripple) toward the output.

Ordering Information

PART NUMBER TEMP. RANGE (

C) PACKAGE

CD54HC40105F3A -55 to 125 16 Ld CERDIP

CD54HCT40105F3A -55 to 125 16 Ld CERDIP

CD74HC40105E -55 to 125 16 Ld PDIP

CD74HC40105M -55 to 125 16 Ld SOIC

CD74HC40105MT -55 to 125 16 Ld SOIC

CD74HC40105M96 -55 to 125 16 Ld SOIC

CD74HCT40105E -55 to 125 16 Ld PDIP

CD74HCT40105M -55 to 125 16 Ld SOIC

CD74HCT40105MT -55 to 125 16 Ld SOIC

CD74HCT40105M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

February 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC40105, CD74HC40105,

CD54HCT40105, CD74HCT40105

High-Speed CMOS Logic

4-Bit x 16-Word FIFO Register

[ /Title

(CD74

HC401

05,

CD74

HCT40

105)

/Sub-

ject

(High

Speed

CMOS

Pinout

CD54HC40105, CD54HCT40105

(CERDIP)

CD74HC40105, CD74HCT40105

(PDIP, SOIC)

TOP VIEW

Loading Data

Data can be entered whenever the DATA-IN READY (DIR)

ﬂag is high, by a low to high transition on the SHIFT-IN (SI)

input. This input must go low momentarily before the next

word is accepted by the FIFO. The DIR ﬂag will go low

momentarily, until the data have been transferred to the sec-

ond location. The ﬂag will remain low when all 16-word loca-

tions are ﬁlled with valid data, and further pulses on the SI

input will be ignored until DIR goes high.

Unloading Data

As soon as the ﬁrst word has rippled to the output, the data-

out ready output (DOR) goes HIGH and data of the ﬁrst word

is available on the outputs. Data of other words can be

removed by a negative-going transition on the shift-out input

(

SO). This negative-going transition causes the DOR signal

to go LOW while the next word moves to the output. As long

as valid data is available in the FIFO, the DOR signal will go

high again, signifying that the next word is ready at the

output. When the FIFO is empty, DOR will remain LOW, and

any further commands will be ignored until a “1” marker

ripples down to the last control register and DOR goes

HIGH. If during unloading SI is HIGH, (FIFO is full) data on

the data input of the FIFO is entered in the ﬁrst location.

Master Reset

A high on the MASTER RESET (MR) sets all the control

logic marker bits to “0”. DOR goes low and DIR goes high.

The contents of the data register are not changed, only

declared invalid, and will be superseded when the ﬁrst word

is loaded. Thus, MR does not clear data within the register

but only the control logic. If the shift-in ﬂag (SI) is HIGH

during the master reset pulse, data present at the input (D0

to D3) are immediately moved into the ﬁrst location upon

completion of the reset process.

Three-State Outputs

In order to facilitate data busing, three-state outputs (Q0 to

Q3) are provided on the data output lines, while the load

condition of the register can be detected by the state of the

DOR output. A HIGH on the three-state control ﬂag (output

enable input OE) forces the outputs into the high-impedance

OFF-state mode. Note that the shift-out signal, unlike that in

the CD40105B, is independent of the three-state output

control. In the CD40105B, the three-state control must not

be shifted from High to Low when the shift-out signal is Low

(data loss would occur). In the high-speed CMOS version

this restriction has been eliminated.

Cascading

The 40105 can be cascaded to form longer registers simply

by connecting the DIR to SO and DOR to SI. In the cascaded

mode, a MASTER RESET pulse must be applied after the

supply voltage is turned on. For words wider than four bits, the

DIR and the DOR outputs must be gated together with AND

gates. Their outputs drive the SI and SO inputs in parallel, if

expanding is done in both directions (see Figures 12 and 13).

Functional Diagram

THREE-STATE

DIR

GND

DOR

CONTROL

STATE

CONTROL

SHIFT OUT

MASTER

SHIFT IN

RESET

DATA-OUT

DATA-IN

READY

GND = 8

= 16

THREE-

CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For V

< -0.5V or V

> V

+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For V

< -0.5V or V

> V

+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For V

> -0.5V or V

< V

+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC V

or Ground Current, I

. . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (T

) . . . . . . . . . . . . . . . . . . . . . -55

C to 125

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

, V

. . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 1) θ

(

C/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . .-65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS

(V)

C -40

C TO 85

C -55

C TO 125

UNITSV

(V) I

(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

or V

-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

or V

0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current

GND

-6--±0.1 - ±1-±1 µA

Quiescent Device

Current

GND

0 6 - - 8 - 80 - 160 µA

CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105

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