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ADC128S102-SEP Radiation-Tolerant, 8-Channel, 50-kSPS to 1-MSPS, 12-Bit ADC

1 Features

• Radiation tolerant:

– Single-event latch-up (SEL) immune up to

LET = 43 MeV-cm

/mg at 125°C

– Single-event functional interrupt (SEFI)

characterized up to LET = 43 MeV-cm

/mg

– Total ionizing dose (TID) characterized up to

30 krad(Si)

– TID RLAT/RHA up to 30 krad(Si)

• Space-enhanced plastic (space EP):

– Meets ASTM E595 outgassing specification

– Vendor item drawing (VID) V62/TBD

– Military temperature range: –55°C to 125°C

– One fabrication, assembly, and test site

– Gold bond wire, NiPdAu lead finish

– Wafer lot traceability

– Extended product life cycle

– Extended product change notification

• Wide supply range:

– V

: 2.7 V to 5.25 V

– V

: 2.7 V to V

• SPI

™

-, QSPI

™

-, MICROWIRE

-, DSP-compatible

• Conversion rate: 50 kSPS to 1 MSPS

• DNL: +1.5 LSB to −0.9 LSB (maximum)

• INL: +1.4 to −1.25 LSB (maximum)

• Power consumption:

– 3-V supply: 2.3 mW (typical)

– 5-V supply: 10.7 mW (typical)

2 Applications

• Voltage, current, and temperature monitoring

• Satellites:

– Attitude and orbit control

– Precision sensors

– Motor control

• Accelerators

3 Description

The ADC128S102-SEP is a low-power, eight-channel,

CMOS, 12-bit analog-to-digital converter (ADC)

specified for conversion throughput rates of 50 kSPS

to 1 MSPS. The converter is based on a successive-

approximation register (SAR) architecture with an

internal track-and-hold circuit. The device can be

configured to accept up to eight input signals at inputs

IN0 through IN7.

The output serial data is straight binary and

compatible with several standards, such as SPI,

QSPI, MICROWIRE, and many common DSP serial

interfaces.

The ADC128S102-SEP can be operated with

independent analog and digital supplies. The analog

supply (V

) can range from 2.7 V to 5.25 V, and the

digital supply (V

) can range from 2.7 V to V

. Normal

power consumption using a 3-V or 5-V supply is

2.3 mW and 10.7 mW, respectively. The power-down

feature reduces the power consumption to 16.5 μW

using a 3-V supply and 30 μW using a 5-V supply.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

ADC128S102-SEP TSSOP (16) 5.00 mm x 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

SAR

ADC

CONTROLLER

IN7

IN6

IN5

IN4

IN3

IN2

IN1

IN0

AGND DGND

4-wire SPI

VIN7

VIN3

VIN0

MCU

VA is used as the Reference

for the ADC

VD can be set independently

of VA

“Digital” Supply Rail“Analog” Supply Rail

Block Diagram

ADVANCE INFORMATION

ADC128S102-SEP

SNAS825 – DECEMBER 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change

without notice.

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Timing Requirements.................................................. 8

6.7 Switching Characteristics............................................8

6.8 Timing Diagrams......................................................... 9

7 Detailed Description......................................................10

7.1 Overview................................................................... 10

7.2 Functional Block Diagram......................................... 10

7.3 Feature Description...................................................10

7.4 Device Functional Modes..........................................12

7.5 Programming............................................................ 12

8 Application and Implementation.................................. 14

8.1 Application Information............................................. 14

8.2 Typical Application.................................................... 14

9 Power Supply Recommendations................................16

9.1 Power-Supply Sequence.......................................... 16

9.2 Power Management..................................................16

9.3 Power-Supply Noise Considerations........................ 16

10 Layout...........................................................................17

10.1 Layout Guidelines................................................... 17

10.2 Layout Example...................................................... 17

11 Device and Documentation Support..........................18

11.1 Receiving Notification of Documentation Updates.. 18

11.2 Support Resources................................................. 18

11.3 Trademarks............................................................. 18

11.4 Electrostatic Discharge Caution.............................. 18

11.5 Glossary.................................................................. 18

12 Mechanical, Packaging, and Orderable

Information.................................................................... 18

12.1 Engineering Samples..............................................18

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE REVISION NOTES

December 2021 * Initial Release

ADC128S102-SEP

SNAS825 – DECEMBER 2021

www.ti.com

ADVANCE INFORMATION

2 Submit Document Feedback

Product Folder Links: ADC128S102-SEP

5 Pin Configuration and Functions

8 9

CS SCLK

DOUT

AGND DIN

IN0 V

IN1 DGND

IN2 IN7

IN3 IN6

IN4 IN5

ADC128S102

Figure 5-1. PW Package, 16-Pin TSSOP (Top View)

Table 5-1. Pin Functions

I/O DESCRIPTION

NO. NAME

1 CS IN

Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as

CS is held low.

2 V

Supply

Positive analog supply pin. This voltage is also used as the reference voltage. Connect this pin to a

quiet 2.7 V to 5.25 V source and bypass this pin to GND with 1-µF and 0.1-µF monolithic ceramic

capacitors located within 1 cm of the power pin.

3 AGND Supply The ground return for the analog supply and signals.

4 IN0 IN Analog input. This signals can range from 0 V to V

REF

5 IN1 IN Analog input. This signals can range from 0 V to V

REF

6 IN2 IN Analog input. This signals can range from 0 V to V

REF

7 IN3 IN Analog input. This signals can range from 0 V to V

REF

8 IN4 IN Analog input. This signals can range from 0 V to V

REF

9 IN5 IN Analog input. This signals can range from 0 V to V

REF

10 IN6 IN Analog input. This signals can range from 0 V to V

REF

11 IN7 IN Analog input. This signals can range from 0 V to V

REF

12 DGND Supply The ground return for the digital supply and signals.

13 V

Supply

Positive digital supply pin. Connect this pin to a 2.7 V to V

supply, and bypass this pin to GND with a

0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin.

14 DIN IN Digital data input. The control register is loaded through this pin on rising edges of the SCLK pin.

15 DOUT OUT

Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK

pin.

16 SCLK IN

Digital clock input. The specified performance range of frequencies for this input is 0.8 MHz to

16 MHz. This clock directly controls the conversion and readout processes.

www.ti.com

ADC128S102-SEP

SNAS825 – DECEMBER 2021

ADVANCE INFORMATION

Submit Document Feedback

Product Folder Links: ADC128S102-SEP

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)

(1)

MIN MAX UNIT

Analog supply voltage (V

) –0.3 6.5 V

Digital supply voltage (V

)

(2)

–0.3 V

+ 0.3 V

Voltage on analog input pins to AGND

(2)

AGND – 0.3 V

+ 0.3 V

Voltage on digital input and digital output pins to DGND

(2)

DGND – 0.3 V

+ 0.3 V

DGND to AGND –0.3 0.3 V

Input current at any pin –10 10 mA

Package input current –20 20 mA

Power-dissipation at T

= 25°C See

(3)

Junction temperature, T

150 °C

Storage temperature, T

stg

–65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) The maximum voltage is not to exceed 6.5 V

(3) The absolute maximum junction temperature (T

max) for this device is 150°C. The maximum allowable power dissipation is dictated

by TJmax, the junction-to-ambient thermal resistance (θ

), and the ambient temperature (T

), and can be calculated using the formula

MAX = (T

max − T

)/θ

. The values for maximum power dissipation listed above will be reached only when the device is operated

in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is

reversed). Such conditions should always be avoided.

6.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins

(1)

±2000

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins

(2)

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

Analog power supply V

to AGND 2.7 5.25 V

Digital power supply V

to DGND 2.7 V

Digital input voltage 0 V

FSR Full-scale analog input range 0 V

Clock frequency 0.8 16 MHz

Ambient temperature –55 25 125 °C

ADC128S102-SEP

SNAS825 – DECEMBER 2021

www.ti.com

ADVANCE INFORMATION

4 Submit Document Feedback

Product Folder Links: ADC128S102-SEP

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