The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
AD7606+Verilog+FPGA+vivado+串口通信 并行 （173个子文件） 
__synthesis_is_complete__ 0B elaborate.bat 923B compile.bat 846B simulate.bat 816B runme.bat 229B runme.bat 229B ad7606_uart.bit 3.86MB xsim_1.c 6KB xsim.dbg 11KB ad7606_uart_routed.dcp 381KB ad7606_uart_placed.dcp 346KB ad7606_uart_opt.dcp 276KB ad7606_uart.dcp 73KB
xsimk.exe 81KB
usage_statistics_webtalk.html 24KB usage_statistics_ext_xsim.html 3KB usage_statistics_ext_labtool.html 3KB .xsim_webtallk.info 64B .xsim_webtallk.info 59B xsimSettings.ini 1KB xsim.ini 40B webtalk_117744.backup.jou 1KB webtalk.jou 1KB vivado_139016.backup.jou 814B vivado_146888.backup.jou 814B vivado_112420.backup.jou 814B vivado.jou 814B vivado.jou 809B ISEWrap.js 7KB ISEWrap.js 7KB rundef.js 1KB rundef.js 1KB runme.log 32KB runme.log 28KB webtalk_117744.backup.log 1KB webtalk.log 1KB elaborate.log 759B compile.log 657B xvlog.log 657B labtool_webtalk.log 402B xsimkernel.log 340B simulate.log 50B xsimcrash.log 0B ad5.lpr 343B xsim.mem 5KB xsim_0.win64.obj 25KB xsim_1.win64.obj 4KB vivado.pb 53KB route_design.pb 12KB place_design.pb 12KB opt_design.pb 11KB write_bitstream.pb 6KB init_design.pb 4KB xelab.pb 2KB xvlog.pb 1KB ad7606_uart_power_summary_routed.pb 722B ad7606_uart_utilization_placed.pb 224B ad7606_uart_utilization_synth.pb 224B vivado.pb 149B ad7606_uart_methodology_drc_routed.pb 53B ad7606_uart_timing_summary_routed.pb 52B ad7606_uart_route_status.pb 44B ad7606_uart_drc_routed.pb 37B ad7606_uart_drc_opted.pb 37B ad7606_uart_bus_skew_routed.pb 30B ad7606_vlg_tst_vlog.prj 276B xsim.reloc 2KB xsim.rlx 797B xil_defaultlib.rlx 551B ad7606_uart_io_placed.rpt 117KB ad7606_uart_methodology_drc_routed.rpt 38KB ad7606_uart_clock_utilization_routed.rpt 11KB ad7606_uart_utilization_placed.rpt 9KB ad7606_uart_power_routed.rpt 8KB ad7606_uart_timing_summary_routed.rpt 7KB ad7606_uart_utilization_synth.rpt 7KB ad7606_uart_control_sets_placed.rpt 6KB ad7606_uart_drc_routed.rpt 2KB ad7606_uart_drc_opted.rpt 2KB ad7606_uart_bus_skew_routed.rpt 909B ad7606_uart_route_status.rpt 588B ad7606_uart_power_routed.rpx 139KB ad7606_uart_methodology_drc_routed.rpx 61KB ad7606_uart_timing_summary_routed.rpx 36KB ad7606_uart_bus_skew_routed.rpx 1KB ad7606_uart_drc_routed.rpx 354B ad7606_uart_drc_opted.rpx 353B .vivado.begin.rst 362B .route_design.begin.rst 183B .opt_design.begin.rst 183B .write_bitstream.begin.rst 183B .place_design.begin.rst 183B .init_design.begin.rst 183B .vivado.begin.rst 182B .init_design.end.rst 0B .vivado.end.rst 0B .Vivado_Implementation.queue.rst 0B .write_bitstream.end.rst 0B .route_design.end.rst 0B .opt_design.end.rst 0B共 173 条
- 1
- 2
资源评论
