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基于FPGA的uart串口通信
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2024-01-17
10:38:55
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uart.zip （87个子文件） 
uart uart.ip_user_files 
README.txt 130B uart.runs impl_1 
runme.bat 229B rundef.js 1KB htr.txt 399B uart_rx.tcl 5KB project.wdf 4KB gen_run.xml 6KB runme.sh 1KB ISEWrap.js 7KB ISEWrap.sh 2KB .jobs vrs_config_1.xml 326B vrs_config_3.xml 326B vrs_config_4.xml 539B vrs_config_2.xml 340B synth_1 runme.bat 229B .vivado.begin.rst 179B __synthesis_is_running__ 0B runme.log 1KB rundef.js 1KB htr.txt 391B .Xil .vivado.error.rst 0B uart_rx.tcl 2KB .Vivado_Synthesis.queue.rst 0B vivado.jou 741B vivado.pb 2KB gen_run.xml 2KB runme.sh 1KB ISEWrap.js 7KB ISEWrap.sh 2KB uart_rx.vds 2KB uart.xpr 9KB rx uart_rx.v.v 2KB uart_rx_tb.v 2KB uart.sim sim_1 behav xsim compile.bat 838B xsim.ini 40B elaborate.bat 915B glbl.v 1KB xvlog.log 558B uart_rx_tb.tcl 460B simulate.log 50B elaborate.log 753B compile.log 558B webtalk.jou 939B webtalk_42820.backup.jou 940B webtalk_6112.backup.log 923B xvlog.pb 1KB webtalk_7804.backup.log 923B uart_rx_tb_vlog.prj 249B webtalk_42820.backup.log 1009B webtalk_7804.backup.jou 854B webtalk.log 1008B xelab.pb 2KB webtalk_6112.backup.jou 854B simulate.bat 804B xsim.dir xil_defaultlib uart_rx_tb.sdb 2KB uart_rx.sdb 5KB xil_defaultlib.rlx 413B glbl.sdb 4KB uart_rx_tb_behav 
xsimk.exe 73KB xsim.rlx 779B obj xsim_1.win64.obj 3KB xsim_1.c 5KB xsim_0.win64.obj 15KB xsim.mem 4KB xsim.type 24B xsimkernel.log 333B xsim.xdbg 1KB xsim.dbg 8KB Compile_Options.txt 254B xsim.rtti 190B webtalk xsim_webtalk.tcl 4KB usage_statistics_ext_xsim.wdm 1KB .xsim_webtallk.info 64B TempBreakPointFile.txt 29B xsim.svtype 39B xsim.reloc 1KB xsimSettings.ini 1KB xsimcrash.log 0B uart_rx_tb_behav.wdb 1GB uart.cache compile_simlib riviera vcs modelsim xcelium ies activehdl questa ip 2018.3 wt xsim.wdf 256B java_command_handlers.wdf 2KB webtalk_pa.xml 6KB project.wpc 61B gui_handlers.wdf 6KB synthesis_details.wdf 100B synthesis.wdf 5KB uart.hw hw_1 wave uart.lpr 343B资源评论
