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基于FPGA的串口通信设计.rar
共123个文件
cdb:14个
hdb:13个
ddb:8个
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2019-05-31
23:18:08
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为了适应全数字自动化控制更加广泛应用,采用FPGA对UART进行多模块的系统设计的方法,是串口通信的集成度更高。对UART系统结构进行了多模块的分解。UART(通用异步收发器)是一种应用广泛的短距离串行传输接口,常用于短距离、低速、低成本的通信中。本文采用了Verilog语言设计了一个UART发送模块和接收模块,从而实现FPGA和PC机的异步串行通信。
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基于FPGA的串口通信设计.rar (123个子文件)
uart_top.vpr.ammdb 477B
uart_top.root_partition.cmp.ammdb 441B
uart_top.map.ammdb 122B
uart_rx.v.bak 2KB
bps.v.bak 2KB
uart_tx.v.bak 1KB
uart_top.v.bak 1KB
uart_top.cmp.bpm 567B
uart_top.map.bpm 539B
uart_top.cmp.cdb 23KB
uart_top.root_partition.cmp.cdb 11KB
uart_top.map.cdb 8KB
uart_top.sgdiff.cdb 8KB
uart_top.root_partition.map.cdb 8KB
uart_top.rtlv_sg.cdb 6KB
uart_top.(1).cnf.cdb 3KB
uart_top.(2).cnf.cdb 3KB
uart_top.(0).cnf.cdb 2KB
uart_top.map_bb.cdb 2KB
uart_top.root_partition.map.hbdb.cdb 1KB
uart_top.(3).cnf.cdb 1KB
uart_top.rtlv_sg_swap.cdb 1KB
uart_top.root_partition.map.reg_db.cdb 198B
logic_util_heursitic.dat 7KB
uart_top.db_info 139B
uart_top.db_info 139B
uart_top.tiscmp.slow_1200mv_0c.ddb 151KB
uart_top.tiscmp.slow_1200mv_85c.ddb 150KB
uart_top.tiscmp.fast_1200mv_0c.ddb 149KB
uart_top.tiscmp.fastest_slow_1200mv_0c.ddb 114KB
uart_top.tiscmp.fastest_slow_1200mv_85c.ddb 114KB
uart_top.asm_labs.ddb 8KB
uart_top.tis_db_list.ddb 234B
uart_top.pti_db_list.ddb 176B
uart_top.root_partition.cmp.dfp 33B
uart_top.done 26B
uart_top.root_partition.map.dpi 963B
uart_top.root_partition.map.hbdb.hb_info 46B
uart_top.cmp.hdb 13KB
uart_top.root_partition.cmp.hdb 13KB
uart_top.map.hdb 12KB
uart_top.root_partition.map.hdb 12KB
uart_top.root_partition.map.hbdb.hdb 12KB
uart_top.pre_map.hdb 12KB
uart_top.rtlv.hdb 12KB
uart_top.sgdiff.hdb 11KB
uart_top.map_bb.hdb 9KB
uart_top.(2).cnf.hdb 1KB
uart_top.(0).cnf.hdb 1KB
uart_top.(1).cnf.hdb 1KB
uart_top.(3).cnf.hdb 804B
uart_top.hier_info 5KB
uart_top.hif 643B
uart_top.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd 729KB
uart_top.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd 728KB
uart_top.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd 723KB
uart_top.lpc.html 1KB
uart_top.cmp.idb 11KB
uart_top.ipinfo 162B
uart_top.jdi 226B
uart_top.root_partition.map.kpt 2KB
uart_top.map.kpt 2KB
uart_top.cmp_merge.kpt 210B
uart_top.root_partition.cmp.kpt 209B
uart_top.cmp.kpt 204B
uart_top.cmp.logdb 8KB
uart_top.map.logdb 4B
uart_top.map_bb.logdb 4B
uart_top.root_partition.cmp.logdb 4B
基于FPGA的串口通信设计.pdf 810KB
uart_top.pin 20KB
prev_cmp_uart_top.qmsg 50KB
uart_top.fit.qmsg 17KB
uart_top.sta.qmsg 16KB
uart_top.map.qmsg 8KB
uart_top.eda.qmsg 5KB
uart_top.asm.qmsg 2KB
uart_top.qpf 1KB
uart_top.qsf 3KB
uart_top.qws 3KB
uart_top.root_partition.cmp.rcfdb 10KB
uart_top.sta.rdb 19KB
uart_top.cmp.rdb 19KB
uart_top.routing.rdb 4KB
uart_top.asm.rdb 1KB
uart_top.map.rdb 1KB
uart_top.lpc.rdb 497B
uart_top.pplq.rdb 231B
README 653B
uart_top.sta.rpt 170KB
uart_top.fit.rpt 118KB
uart_top.map.rpt 25KB
uart_top.flow.rpt 8KB
uart_top.eda.rpt 7KB
uart_top.asm.rpt 7KB
uart_top.sld_design_entry_dsc.sci 201B
uart_top.sld_design_entry.sci 201B
uart_top_8_1200mv_85c_v_slow.sdo 73KB
uart_top_v.sdo 73KB
uart_top_8_1200mv_0c_v_slow.sdo 73KB
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- 野生程序员vip2020-10-23感觉还可以吧
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