///////////////////////////////////////////////////////////////////////////////
//
// Company: Xilinx
// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
// Date: 10/24/2014
// Design Name: MMCME2 DRP
// Module Name: mmcme2_drp_func.h
// Version: 1.30
// Target Devices: 7 Series
// Tool versions: 2014.3
// Description: This header provides the functions necessary to
// calculate the DRP register values for the V6 MMCM.
//
// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR)
// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
// 10/24- Adjusting settings for clarity
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2009-2010 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
// These are user functions that should not be modified. Changes to the defines
// or code within the functions may alter the accuracy of the calculations.
// Define debug to provide extra messages durring elaboration
`define DEBUG 1
// FRAC_PRECISION describes the width of the fractional portion of the fixed
// point numbers. These should not be modified, they are for development
// only
`define FRAC_PRECISION 10
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
// greater than 32
`define FIXED_WIDTH 32
// This function takes a fixed point number and rounds it to the nearest
// fractional precision bit.
function [`FIXED_WIDTH:1] round_frac
(
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
input [`FIXED_WIDTH:1] decimal,
// This describes the precision of the fraction, for example a value
// of 1 would modify the fractional so that instead of being a .16
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
input [`FIXED_WIDTH:1] precision
);
begin
`ifdef DEBUG
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
`endif
// If the fractional precision bit is high then round up
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
end else begin
round_frac = decimal;
end
`ifdef DEBUG
$display("round_frac: %h", round_frac);
`endif
end
endfunction
// This function calculates high_time, low_time, w_edge, and no_count
// of a non-fractional counter based on the divide and duty cycle
//
// NOTE: high_time and low_time are returned as integers between 0 and 63
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
// ignore the overflow)
function [13:0] mmcm_divider
(
input [7:0] divide, // Max divide is 128
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
);
reg [`FIXED_WIDTH:1] duty_cycle_fix;
// High/Low time is initially calculated with a wider integer to prevent a
// calculation error when it overflows to 64.
reg [6:0] high_time;
reg [6:0] low_time;
reg w_edge;
reg no_count;
reg [`FIXED_WIDTH:1] temp;
begin
// Duty Cycle must be between 0 and 1,000
if(duty_cycle <=0 || duty_cycle >= 100000) begin
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
$finish;
end
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
`ifdef DEBUG
$display("duty_cycle_fix: %h", duty_cycle_fix);
`endif
// If the divide is 1 nothing needs to be set except the no_count bit.
// Other values are dummies
if(divide == 7'h01) begin
high_time = 7'h01;
w_edge = 1'b0;
low_time = 7'h01;
no_count = 1'b1;
end else begin
temp = round_frac(duty_cycle_fix*divide, 1);
// comes from above round_frac
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
// If the duty cycle * divide rounded is .5 or greater then this bit
// is set.
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
// If the high time comes out to 0, it needs to be set to at least 1
// and w_edge set to 0
if(high_time == 7'h00) begin
high_time = 7'h01;
w_edge = 1'b0;
end
if(high_time == divide) begin
high_time = divide - 1;
w_edge = 1'b1;
end
// Calculate low_time based on the divide setting and set no_count to
// 0 as it is only used when divide is 1.
low_time = divide - high_time;
no_count = 1'b0;
end
// Set the return value.
mmcm_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
end
endfunction
// This function calculates mx, delay_time, and phase_mux
// of a non-fractional counter based on the divide and phase
//
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
// is used.
function [10:0] mmcm_phase
(
// divide must be an integer (use fractional if not)
// assumed that divide already checked to be valid
input [7:0] divide, // Max divide is 128
// Phase is given in degrees (-360,000 to 360,000)
input signed [31:0] phase
);
reg [`FIXED_WIDTH:1] phase_in_cycles;
reg [`FIXED_WIDTH:1] phase_fixed;
reg [1:0] mx;
reg [5:0] delay_time;
reg [2:0] phase_mux;
reg [`FIXED_WIDTH:1] temp;
begin
`ifdef DEBUG
$display("mmcm_phase-divide:%d,phase:%d",
divide, phase);
`endif
if ((phase < -360000) || (phase > 360000)) begin
$display("ERROR: phase of $phase is not between -360000 and 360000");
$finish;
end
// If phase is less than 0, convert it to a positive phase shift
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
if(phase < 0) begin
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
end else begin
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
end
// Put phase in terms of decimal number of vco clock cycles
phase_in_cycles = ( phase_fixed * divide ) / 360;
`ifdef DEBUG
$display("phase_in_cycles: %h", phase_in_cycles);
`endif
AD9689_ADS7v2.zip （158个子文件） 
ad9689_ads7v2.bin 13.26MB ncsim_run.do 55B mmcme2_drp_func.h 24KB ignore_list 272B Makefile 12KB Makefile 9KB Makefile 7KB embedded_build.mk 2KB defaults.mk 813B microblaze_opts.mk 610B helper.mk 436B sim_opts.mk 417B fpga_opts.mk 291B mig_b.prj 17KB mig_a.prj 17KB prep_mem.py 6KB raw_mem.py 5KB append_data.py 2KB strip_yoda_comments.sh 653B setup.sh 88B fpga_dig_top.sv 51KB main_memory_top.sv 26KB main_memory_top.sv 24KB mig_ui_data_and_hist.sv 22KB main_memory_ddr3.sv 20KB main_memory_ddr3_dual.sv 17KB mig_ui_histogram.sv 14KB jesd204_axi_reg_read.sv 13KB tb_mig_ui_data_and_hist.sv 10KB main_memory_ddr3_tb.sv 8KB axi_lite_stim_master.sv 8KB gt_error_count.sv 7KB mig_ui_tester.sv 5KB mig_ui_fifo.sv 5KB tb_mig_ui_histogram.sv 4KB width_convert_up.sv 4KB width_convert_down.sv 4KB mig_ui_fifo_tb.sv 3KB mig_ui_ram.sv 3KB bf_handshake_rd_dual.sv 3KB axi4.sv 3KB bf_handshake_rd_mux.sv 3KB s_axis_to_s_axi.sv 2KB axi4_lite.sv 2KB ddr_meas.sv 1KB simple_xbar.sv 945B vivado_helper.tcl 19KB timing_exceptions.tcl 13KB svn_rev.tcl 2KB timing.tcl 2KB timing_exceptions_impl.tcl 2KB build_simenv.tcl 1KB generate_smapx32_bit.tcl 623B copy_bin.tcl 570B pulse_sync.tcl 529B generate_spix8_bit.tcl 508B run_sdk.tcl 438B generate_bin.tcl 148B build_hw.tcl 147B generate_spi_mcs.tcl 132B build_sdk.tcl 124B bus_sync.tcl 96B build_complib_ies.tcl 76B reset_sync.tcl 59B mig_ui_data_and_hist.tv 4KB basic_test.tv 3KB mig_ui_histogram.tv 2KB mig_ui_fifo_all_wr.tv 1KB main_memory_ddr3_default.tv 861B ddr1_micron_1600_noaxi_sim_netlist.v 10.14MB fifo_async_512x512_sim_netlist.v 290KB fifo_async_512x512_sim_netlist.v 290KB v7_gth_gt.v 50KB axis_mux.v 39KB sample_assembly.v 23KB spi_master_logic.v 18KB v7_gth.v 18KB mmcme2_drp.v 17KB jesd204_top.v 17KB spi_fpga.v 17KB tb_fpga_dig_top.v 16KB dut_format.v 13KB spi_master_bufctl.v 13KB spi_master_regmap.v 12KB gt_drp_ctrl.v 11KB bf_handshake_rd.v 10KB axi4_lite_simple_master.v 10KB axis_regslice.v 9KB bf_handshake_rd_dual_ddr.v 9KB jesd204_frame_align.v 9KB jesd204_axi_error_check.v 8KB main_memory_bram_fifo.v 8KB jesd204_register_config.v 8KB freq_counter.v 7KB bf_handshake_wr.v 7KB sys_clk_top.v 7KB qpll_drp_ctrl.v 7KB spi_master_top.v 7KB sys_clk_ctrl.v 7KB jesd204_ip_top.v 6KB共 158 条
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