基于verilog语言和vivado实现的ad9613数字采集工程

2015.2: * Version 5.1 (Rev. 7) * Internal device family change, no functional changes 2015.1: * Version 5.1 (Rev. 6) * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices * Supported devices and production status are now determined automatically, to simplify support for future devices 2014.4.1: * Version 5.1 (Rev. 5) * No changes 2014.4: * Version 5.1 (Rev. 5) * Internal device family change, no functional changes * updates related to the source selection based on board interface for zed board 2014.3: * Version 5.1 (Rev. 4) * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 2014.2: * Version 5.1 (Rev. 3) * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 2014.1: * Version 5.1 (Rev. 2) * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock * Internal device family name change, no functional changes 2013.4: * Version 5.1 (Rev. 1) * Added support for Ultrascale devices * Updated Board Flow GUI to select the clock interfaces * Fixed issue with Stub file parameter error for BUFR output driver 2013.3: * Version 5.1 * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies * Fixed precision issues between displayed and actual frequencies * Added tool tips to GUI * Added Jitter and Phase error values to IP properties * Added support for Cadence IES and Synopsys VCS simulators * Reduced warnings in synthesis and simulation * Enhanced support for IP Integrator 2013.2: * Version 5.0 (Rev. 1) * Fixed issue with clock constraints for multiple instances of clocking wizard * Updated Life-Cycle status of devices 2013.1: * Version 5.0 * Lower case ports for Verilog * Added Safe Clock Startup and Clock Sequencing (c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws. DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail- safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.