xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2017.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/d618/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/f9cc/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/ecd6/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/ce23/hdl/verilog"
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2017.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/d618/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/f9cc/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/ecd6/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/ce23/hdl/verilog"
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2017.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/d618/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/f9cc/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/ecd6/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/ce23/hdl/verilog"
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/d618/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/f9cc/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/ecd6/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/ce23/hdl/verilog"
xil_common_vip_v1_0_vl_rfs.sv,systemverilog,xil_common_vip_v1_0_0,../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl/xil_common_vip_v1_0_vl_rfs.sv,incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/d618/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/f9cc/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/ecd6/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/ce23/hdl/verilog"
sc_util_v1_0_vl_rfs.sv,systemverilog,smartconnect_v1_0,../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/sc_util_v1_0_vl_rfs.sv,incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="$ref_dir/../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/7e3a/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/2ad9/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/39ca/hdl/verilog"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/6eb1/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sources_1/bd/design_1/ipshared/1d61/hdl"incdir="../../../../DDR_data_to_PL_v4.srcs/sou
如何将DDR的数据传给PL端
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2021-07-19
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如何将DDR的数据传给PL端 （1027个子文件） 
libxil.a 262KB runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B runme.bat 229B design_1.bd 68KB bd_f60c.bd 18KB bd_f60c.bd 18KB top.bit 1.99MB top.bit 1.99MB design_1.bxml 6KB bd_f60c.bxml 3KB ps7_init.c 563KB ps7_init.c 563KB ps7_init_gpl.c 562KB ps7_init_gpl.c 562KB xadcps.c 54KB xsdps_options.c 52KB xdmaps.c 52KB xaxidma_bdring.c 51KB xsdps.c 50KB xqspips.c 49KB xil_cache.c 45KB xusbps_endpoint.c 42KB xemacps_control.c 40KB xemacps_bdring.c 37KB xscugic.c 31KB xdevcfg.c 29KB xaxidma.c 26KB xgpiops_intr.c 25KB xuartps_options.c 24KB xuartps.c 22KB xgpiops.c 21KB xil_testmem.c 20KB xscugic_hw.c 19KB xemacps.c 17KB xil_misc_psreset_api.c 16KB xqspips_options.c 14KB xuartps_intr.c 14KB xusbps_intr.c 14KB xusbps.c 12KB _profile_timer_hw.c 12KB xaxidma_bd.c 11KB xil_printf.c 11KB xil_exception.c 10KB xemacps_intr.c 10KB xil_testcache.c 10KB xdevcfg_intr.c 9KB xil_testio.c 8KB xscutimer.c 8KB xadcps_intr.c 8KB xpm_counter.c 8KB xscuwdt.c 7KB xscugic_intr.c 7KB vectors.c 7KB xqspips_hw.c 7KB xil_mmu.c 6KB xuartps_selftest.c 6KB xgpiops_hw.c 6KB xuartps_hw.c 6KB xl2cc_counter.c 6KB xcoresightpsdcc.c 6KB xil_assert.c 5KB xemacps_hw.c 5KB xscutimer_selftest.c 5KB profile_cg.c 5KB xqspips_selftest.c 5KB xgpiops_selftest.c 5KB xtime_l.c 4KB xdevcfg_hw.c 4KB xadcps_selftest.c 4KB xscuwdt_selftest.c 4KB xusbps_hw.c 4KB xplatform_info.c 4KB xdmaps_hw.c 4KB xdevcfg_selftest.c 4KB xscugic_selftest.c 4KB xscugic_sinit.c 4KB xdmaps_selftest.c 4KB xgpiops_sinit.c 4KB xsdps_sinit.c 4KB xscutimer_sinit.c 4KB xemacps_sinit.c 4KB xscuwdt_sinit.c 4KB xadcps_sinit.c 4KB xuartps_sinit.c 4KB xqspips_sinit.c 4KB xaxidma_selftest.c 4KB xusbps_sinit.c 3KB xil_io.c 3KB xdmaps_sinit.c 3KB xdevcfg_sinit.c 3KB xaxidma_sinit.c 3KB usleep.c 3KB platform.c 3KB共 1027 条
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