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All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
R-Car H3 / M3
User’s Manual: Hardware
Rev.0.10 Decembe
r
2020
SoCs for Automotive Information Terminal Applications
R-Car Family / R-Car Gen3 Series
— Preliminary
—
For H3/M3 Starter Kit
User’ s Manual
www.ren es as. com
© 2020 Renesas Electronics Corporation. All rights reserved.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products
and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your
product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of
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General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be
touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in
a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level
at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements.
Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced
with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V
IL
(Max.)
and V
IH
(Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level
is fixed, and also in the transition period when the input level passes through the area between V
IL
(Max.) and V
IH
(Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of
internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-
evaluation test for the given product.
Contents
1. Overview ...................................................................................................................................... 1-1
1.1 Introduction ............................................................................................................................................................ 1-1
1.2 List of Specifications ............................................................................................................................................. 1-2
1.2.1 Arm Core ..................................................................................................................................................... 1-2
1.2.4 External Bus Module ................................................................................................................................... 1-3
1.2.5 Internal Bus Module .................................................................................................................................... 1-4
1.2.6 Internal Memory .......................................................................................................................................... 1-5
1.2.7 Graphics Units ............................................................................................................................................. 1-6
1.2.8 Video Processing ......................................................................................................................................... 1-9
1.2.9 Sound Interface ......................................................................................................................................... 1-15
1.2.10 Storage....................................................................................................................................................... 1-16
1.2.11 Network ..................................................................................................................................................... 1-17
1.2.12 Timer ......................................................................................................................................................... 1-17
1.2.13 Peripheral Module ..................................................................................................................................... 1-18
2. Area Map ..................................................................................................................................... 2-1
12A. Interrupt Controller (INTC-AP) ......................................................................................... 12A-1
12A.1 Overview ........................................................................................................................................................... 12A-1
12A.1.1 Features .................................................................................................................................................. 12A-1
12A.1.2 Block Diagram ....................................................................................................................................... 12A-1
12A.1.3 External Pins .......................................................................................................................................... 12A-1
12A.1.4 Register Configuration ........................................................................................................................... 12A-1
12A.1.5 Connected Module ................................................................................................................................. 12A-2
12A.2 Register Description .......................................................................................................................................... 12A-3
12A.3 Operation .......................................................................................................................................................... 12A-4
12A.3.1 INTC-AP Register Configuration and Function Description ................................................................. 12A-4
12A.3.2 Interrupts Mapping ................................................................................................................................. 12A-5
13. Interrupt Controller (INTC-EX) .............................................................................................. 13-1
13.1 Overview .............................................................................................................................................................. 13-1
13.1.1 Features ..................................................................................................................................................... 13-1
13.1.2 Block Diagram .......................................................................................................................................... 13-1
13.1.3 External Pins ............................................................................................................................................. 13-2
13.1.4 Register Configuration .............................................................................................................................. 13-2
13.1.5 Connected Module .................................................................................................................................... 13-5
13.2 Register Description ............................................................................................................................................. 13-6
13.2.1 Interrupt Request Status Register0 (INTREQ_STS0) ............................................................................... 13-6
13.2.2 Interrupt Enable Status Register0 (INTEN_STS0) ................................................................................... 13-7
13.2.3 Interrupt Enable Set Register0 (INTEN_SET0) ........................................................................................ 13-8
13.2.4 IRQn Detect Status Register (DETECT_STATUS) .................................................................................. 13-9
13.2.5 IRQn Signal Level Monitor Register (MONITOR) ................................................................................ 13-10
13.2.6 IRQn High Level Detect Status Register (HLVL_STS) .......................................................................... 13-11
13.2.7 IRQn Low Level Detect Status Register (LLVL_STS) ........................................................................... 13-12
13.2.8 IRQn Sync Rising Edge Detect Status Register (S_R_EDGE_STS) ...................................................... 13-13
13.2.9 IRQn Sync Falling Edge Detect Status Register (S_F_EDGE_STS) ...................................................... 13-14
13.2.10 IRQn Async Rising Edge Detect Status Register (A_R_EDGE_STS) ................................................... 13-15
13.2.11 IRQn Async Falling Edge Detect Status Register (A_F_EDGE_STS) ................................................... 13-16
13.2.12 IRQn Chattering Reduction Status Register (CHTEN_STS) .................................................................. 13-17
13.2.13 IRQn Configuration Register (CONFIG_n) ............................................................................................ 13-18
13.2.14 NMI Request Status Register 0 (NMIREQ_STS0) ................................................................................. 13-20
13.2.15 NMI Enable Status Register 0 (NMIEN_STS0) ...................................................................................... 13-22
13.2.16 NMI Enable Set Register 0 (NMIEN_SET0) .......................................................................................... 13-24
13.2.17 NMI Detect Status Register (DETECT_STATUS_NMI) ....................................................................... 13-26
13.2.18 NMI Signal Level Monitor Register (MONITOR_NMI) ........................................................................ 13-30
13.2.19 NMI High Level Detect Status Register (HLVL_STS_NMI) ................................................................. 13-33
13.2.20 NMI Low Level Detect Status Register (LLVL_STS_NMI) .................................................................. 13-35
13.2.21 NMI Sync Rising Edge Detect Status Register (S_R_EDGE_STS_NMI) .............................................. 13-37
13.2.22 NMI Sync Falling Edge Detect Status Register (S_F_EDGE_STS_NMI) ............................................. 13-39
13.2.23 NMI Async Rising Edge Detect Status Register (A_R_EDGE_STS_NMI) ........................................... 13-41
13.2.24 NMI Async Falling Edge Detect Status Register (A_F_EDGE_STS_NMI) .......................................... 13-43
13.2.25 NMI Chattering Reduction Status Register (CHTEN_STS_NMI) .......................................................... 13-45
13.2.26 NMI Debounce Setting Register (DEB_SET_NMI) ............................................................................... 13-46
13.2.27 NMI Configuration n Register (CONFIGn_NMI) .................................................................................. 13-47
13.2.28 NMI Mask Lock Set Register (NMI_LCK) ............................................................................................ 13-48
13.2.29 NMI Lock Code Register (NMI_LCKCODE) ........................................................................................ 13-48
13.2.30 NMI Debug Control Enable Register (NMI_DBG) ................................................................................ 13-49
13.2.31 NMI Debug Code Register (NMI_DBGCODE) ..................................................................................... 13-49
13.3 Operation ........................................................................................................................................................... 13-50
13.3.1 NMI Mask Lock Feature ......................................................................................................................... 13-50
13.3.2 Procedure of NMI Mask Lock ................................................................................................................. 13-50
15. AXI-bus .................................................................................................................................... 15-1
15.1 Overview .............................................................................................................................................................. 15-1
15.1.1 Features ..................................................................................................................................................... 15-1
17. Direct Memory Access Controller for System (SYS-DMAC) ................................................ 17-1
17.1 Overview .............................................................................................................................................................. 17-1
17.1.1 Features ..................................................................................................................................................... 17-1
17.1.2 External Pins ............................................................................................................................................. 17-2
17.1.3 Register Configuration .............................................................................................................................. 17-3
17.1.4 Connected Module .................................................................................................................................. 17-31
17.2 Register Description ........................................................................................................................................... 17-32
17.2.1 DMA Interrupt Status Register for channels 0 to 15 (DMAISTA_0) ..................................................... 17-32
17.2.2 DMA Interrupt Status Register for channels 16 to 31 (DMAISTA_1) ................................................... 17-34
17.2.3 DMA Interrupt Status Register for channels 32 to 47 (DMAISTA_2) ................................................... 17-36
17.2.7 DMA Operation Register for channels 0 to 15 (DMAOR_0) ................................................................. 17-38
17.2.8 DMA Operation Register for channels 16 to 31 (DMAOR_1) ............................................................... 17-40
17.2.9 DMA Operation Register for channels 32 to 47 (DMAOR_2) ............................................................... 17-42
17.2.10 DMA Channel Clear Register for channels 0 to 15 (DMACHCLR_0) ................................................... 17-44
17.2.11 DMA Channel Clear Register for channels 16 to 31 (DMACHCLR_1) ................................................. 17-45
17.2.12 DMA Channel Clear Register for channels 32 to 47 (DMACHCLR_2) ................................................. 17-46
17.2.16 DMA Source Address Registers 0 to 47 (DMASAR_0 to DMASAR_47) ............................................. 17-47
17.2.17 DMA Destination Address Registers 0 to 47 (DMADAR_0 to DMADAR_47) .................................... 17-47
17.2.18 DMA Transfer Count Registers 0 to 47 (DMATCR_0 to DMATCR_47) .............................................. 17-48
17.2.19 DMA Transfer Count Registers B_0 to 47 (DMATCRB_0 to DMATCRB_47) .................................... 17-48
17.2.20 DMA Transfer Size Registers 0 to 47 (DMATSR_0 to DMATSR_47) .................................................. 17-49
17.2.21 DMA Transfer Size Registers B_0 to 47 (DMATSRB_0 to DMATSRB_47) ........................................ 17-49
17.2.22 DMA Channel Control Registers 0 to 47 (DMACHCR_0 to DMACHCR_47)...................................... 17-50
17.2.23 DMA Channel Control Register B_0 to 47 (DMACHCRB_0 to DMACHCRB_47) ............................. 17-54
17.2.24 DMA Buffer Control Registers 0 to 47 (DMABUFCR_0 to DMABUFCR_47) .................................... 17-55
17.2.25 DMA Extended Resource Selectors 0 to 47 (DMARS_0 to DMARS_47) ............................................. 17-56
17.2.26 DMA Descriptor Base Address Registers 0 to 47 (DMADPBASE_0 to DMADPBASE_47) ................ 17-57
17.2.27 DMA Descriptor Control Registers 0 to 47 (DMADPCR_0 to DMADPCR_47) ................................... 17-58
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