没有合适的资源?快使用搜索试试~ 我知道了~
Session_30_Power_Management_Techniques.pdf
需积分: 5 0 下载量 54 浏览量
2023-03-14
12:03:18
上传
评论
收藏 27.62MB PDF 举报
温馨提示
试读
32页
Session_30_Power_Management_Techniques.pdf
资源推荐
资源详情
资源评论
Session 30 Overview: Power Management Techniques
POWER MANAGEMENT SUBCOMMITTEE
2:00 PM
30.2 A 93.2%-Efficiency Multi-Input Bipolar Energy Harvester with 17.9× MPPT Loss Reduction
Cheng-Wen Chen,
National Yang Ming Chiao Tung University, Hsinchu, Taiwan
In Paper 30.2, National Yang Ming Chiao Tung University, Chip-GaN Power Semiconductor, and Realtek Semiconductor present
a multi-input bipolar energy harvester with ultra-low-power comparator and zero current detection (ZCD) to achieve low input-
voltage ripple, high accuracy, and 93.2% end-to-end efficiency.
2:30 PM
30.3 A Bias-Flip Rectifier with a Duty-Cycle-Based MPPT Algorithm for Piezoelectric Energy Harvesting with 98% Peak
MPPT Efficiency and 738% Energy-Extraction Enhancement
Xinling Yue,
Delft University of Technology, Delft, The Netherlands
In Paper 30.3, Delft University of Technology presents a new duty-cycle-based MPPT algorithm, validated in a piezoelectric energy
harvesting system with a bias-flip rectifier, that achieves 98% peak MPPT efficiency and 738% power-extraction enhancement
compared to a passive rectifier.
2:45 PM
30.4 A 3.7V-to-1kV Chip-Cascaded Switched-Capacitor Converter with Auxiliary Boost Achieving >96% Reactive Power
Efficiency for Electrostatic Drive Applications
Yanqiao Li,
Dartmouth College, Hanover, NH
In Paper 30.4, Dartmouth College presents a modular/scalable switched capacitor (SC) converter with integrated auxiliary boost
converter for high-voltage electrostatic and piezoelectric (PZT) actuators. With 3 chips stacked, the design provides up to 1kV
pp
from 3.7V battery input (VCR>270), delivering and recovering >1W reactive power at >96% efficiency.
Power-management techniques have been adopted to improve the system performance of emerging power-converter applications such as
energy harvesting, high-voltage actuation, step-up-and-down power supply, and wireless power transfer (WPT). Efficient synchronized-switch
harvesting-on-inductor (SSHI) extraction technique, maximum power point tracking, ultra-wide conversion ratio, scalable multi-chip stackable
bias-flip technique, various DC-DC converters topologies (hybrid, buck-boost, switched capacitor), and advanced WPT systems are presented
in this session to demonstrate the state-of-the-art performance of these power management systems.
Session Chair: Xun Liu
Chinese University of Hong Kong
Shenzhen, China
Session Co-Chair: Gael Pillonnet
CEA-Léti, Grenoble, France
436
• 2023 IEEE International Solid-State Circuits Conference
ISSCC 2023 / SESSION 30 / POWER MANAGEMENT TECHNIQUES / OVERVIEW
978-1-6654-9016-0/23/$31.00 ©2023 IEEE
1:30 PM
30.1 A Scalable N-Step Equal Split SSHI Piezoelectric Energy Harvesting Circuit Achieving 1170% Power Extraction
Improvement and 22nA Quiescent Current with a 1μH-to-10μH Low Q Inductor
Yeon-Woo Jeong, Ulsan National Institute of Science and Technology, Ulsan, Korea
In Paper 30.1, Ulsan National Institute of Science and Technology presents a scalable N-step equal split SSHI that achieves an
energy power extraction of 1170% with a low-Q 1µH inductor. This work operates with 91% flip efficiency and scalable 4-to-16
steps, and consumes only 22nA in its sleep mode.
4:00 PM
30.7 A Continuously Scalable-Conversion-Ratio SC Converter with Reconfigurable VCF Step for High Efficiency over
an Extended VCR Range
Yuanfei Wang,
University of Macau, Macau, China
In Paper 30.7, University of Macau, Zhuhai UM Science & Technology Research Institute, and Instituto Superior
Tecnico/University of Lisboa reconfigure VCF steps at different VCRs in continuously scalable-conversion-ratio SC (CSC)
converters to achieve an optimum efficiency under limited resources. It achieves a 90% peak efficiency with 34 VCF steps and
the widest VCR range with a 75% efficiency.
4:15 PM
30.8 3D Wireless Power Transfer with Noise Cancellation Technique for –62dB Noise Suppression and 90.1%
Efficiency
Hsing-Yen Tsai, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
In Paper 30.8, National Yang Ming Chiao Tung University, Chip-GaN Power Semiconductor, and Realtek Semiconductor present
a 3D wireless power transfer (WPT) system, including 3TXs and one central controller to arrange the power transfer according
to the position of the RX. The design uses a noise cancellation technique to enhance the received signal by 52% with an auxiliary
coil.
4:45 PM
30.9 A 90%-Efficiency 40.68MHz Single-Stage Dual-Output Regulating Rectifier with ZVS and Synchronous PFM
Control for Wireless Powering
Ziyang Luo,
University of Texas at Dallas, Richardson, TX
In Paper 30.9, University of Texas at Dallas presents a 40.68MHz single-stage dual-output regulating rectifier composed of only
3 active diodes to achieve the highest resonance frequency, the smallest RX coil size, and a competitive power efficiency of
90.1%. Synchronous PFM control is developed to provide fast load transient responses with unnoticeable output cross regulation.
5:00 PM
30.10 Single-Chip Qi-Compliant 40W Wireless-Power-Transmission Controller using RMS Coil Current Sensing and
Adaptive ZVS for 4dB EMI and up to 1.7% Efficiency Improvements
Filippo Neri,
Renesas Electronics, Zürich, Switzerland
In Paper 30.10, Renesas Electronics presents a single-chip Qi-compliant 40W wireless-power-transmission controller,
implementing dual RMS and DC current sensing, and adaptive ZVS method to increase the EMI figure by 4dB and to improve
the efficiency by up to 1.7%.
3:45 PM
30.6 A 98.6%-Peak-Efficiency 1.47A/mm
2
-Current-Density Buck-Boost Converter with Always Reduced Conduction
Loss
Ji Jin,
University of Science and Technology of China, Hefei, China
In Paper 30.6, University of Science and Technology of China and Hefei CLT Microelectronics present a flying-capacitor-assisted
buck-boost converter with only 4 switches (which are all immune from voltage stress issue) to reduce the average inductor
current and to achieve 98.6% peak efficiency and 1.47A/mm
2
on-die current density.
ISSCC 2023 / February 22, 2023 / 1:30 PM
437 DIGEST OF TECHNICAL PAPERS •
3:15 PM
30.5 A 95.3% 5V-to-32V Wide Range 3-Level Current Mode Boost Converter with Fully State-based Phase Selection
Achieving Simultaneous High-Speed V
CF
Balancing and Smooth Transition
Seung-Ju Lee,
Ulsan National Institute of Science and Technology, Ulsan, Korea
In Paper 30.5, Ulsan National Institute of Science and Technology and Samsung Electronics present a 3-level boost converter
with a fully state-based phase selection technique and an adaptive slope generator to select the operation mode, balance the
flying capacitor voltage and smoothen the mode transition, which achieves a high efficiency (~95.3%) and a wide output range
(5 to 32V).
30
438
• 2023 IEEE International Solid-State Circuits Conference
ISSCC 2023 / SESSION 30 / POWER MANAGEMENT TECHNIQUES / 30.1
30.1 A Scalable N-Step Equal Split SSHI Piezoelectric Energy
Harvesting Circuit Achieving 1170% Power Extraction
Improvement and 22nA Quiescent Current with a 1μH-to-10μH
Low Q Inductor
Yeon-Woo Jeong, Seung-Ju Lee, Jong-Hun Kim, Mun-Jung Cho,
Hwa-Soo Kim, Se-Un Shin
Ulsan National Institute of Science and Technology, Ulsan, Korea
Energy harvesting with a piezoelectric transducer (PT) converts ambient mechanical
energy into AC electrical energy and can be a solution to various power issues related to
the self-powered systems. The simplest way to harvest AC energy is to apply a full-bridge
rectifier (FBR). However, the FBR causes a sinusoidal current of the PT (I
P
) to
charge/discharge the inherent capacitor of the PT (C
P
) whenever the I
P
direction changes,
resulting in a large charge loss. To address this issue, synchronized-switch harvesting-
on-inductor (SSHI) and synchronous electric-charge extraction (SECE) techniques have
been proposed. The conventional SSHI reduces the charge loss by using the bias flip
technique, which inverts the voltage across the C
P
(V
PT
) with LC
P
resonance [1] (Fig.
30.1.1, top left). Although it increases the extracted power and the voltage of the
maximum power point compared to the FBR, an expensive and large inductor (L) with a
high quality factor (Q) is required for high flip efficiency (η
Flip
). Otherwise, if a low Q
inductor is adopted, a half-cycle resonance flip requires both an accurate zero current
detector (ZCD) and a large inductor current (I
L
), which cause large controller loss and
conduction loss (P
C
), respectively. Similarly, the SECE uses a quarter-cycle resonance,
which requires a high Q inductor as well [2]. Also, a synchronized-switch harvesting-
on-capacitor (SSHC) has also been proposed [3] (Fig. 30.1.1, bottom left). Using a
commercial PT, not custom MEMS, the SSHC needs off-chip capacitors with several
tens of nF, similar to the C
P
of a commercial PT. Because hard charging of the capacitor
incurs a large redistribution loss, the flip process must be split, which requires numerous
off-chip capacitors. Moreover, an adaptive control according to the operating point of
the PT is impossible due to the fixed split phase, which is determined in the design stage.
Structures that split the flip process with a relatively small inductor have also been
proposed [4–6]. However, their precise half-cycle resonance flip requires accurate ZCD
and limits their ability to reduce the inductor to less than tens of H. Also, they need
multiple controllers with large quiescent current (I
Q
) for different duties and use a
considerable number of power elements, such as switches and diodes.
As shown in Fig. 30.1.1, this paper proposes a scalable N-step equal split SSHI (ES-
SSHI) for higher power extraction with a low Q inductor to solve the trade-off issue
between the extracted power and Q. The equally split (ES) flip has following three
advantages. 1) Regular and symmetric duties for each step allow both multiple duty
generation by a single circuit and prediction of zero crossing point of I
L
. They reduce the
controller loss considerably. 2) The ES flip does not use the resonance that requires an
accurate ZCD. Finally, 3) It makes the peak of I
L
(I
L_peak
) lower and constant, increasing
η
Flip
with low P
C
. In addition, a scalable N-step enables an adaptive control according to
the operating point of the PT. Consequently, this work improves power extraction even
with a small inductor (1H to 10H), allowing higher power extraction at a low cost and
with a low volume.
Figure 30.1.2 shows the operation principle of the proposed scalable N-step ES-SSHI.
Depending on I
P
, there are non-flip operation (I
P
>0, I
P
<0) and flip operation (I
P
≈0). In Φ
P
(I
P
>0) of the non-flip operation, I
P
charges C
P
until V
LP
reaches V
BAT
+V
D
, after which I
P
is
harvested to V
BAT
. When I
P
≈0, the flip process is equally split into scalable N-steps to
invert V
PT
. Figure 30.1.2, top right shows flip sequence and operation when I
P
changes
from positive to negative (Φ
P
→Φ
N
). The flip operation is divided into an extracting mode
(Φ
E
) to decrease V
PP
to 0V and an investing mode (Φ
I
) to increase V
PN
to V
BAT
+V
D
. With
the N
flip
steps in each mode, an entire flip operation has 2×N
flip
steps. In Φ
E1
, the energy
of C
P
is transferred to L, and I
L
rises. In Φ
E2
, the energy of C
P
and L is transferred to V
BAT
together, and I
L
falls. After Φ
E1
and Φ
E2
are repeated N
flip
times, V
PP
converges to 0V by
the ES flip, eliminating the need of a half-cycle resonance. Given that several mV of V
PP
,
which may remain due to a controller mismatch, can affect Φ
I
, S
1
and S
2
are turned on
to reset C
P
. Subsequently, Φ
I
, which is symmetrical to Φ
E,
increases V
PN
. At the end of
Φ
I
, the non-flip operation restarts, and the operation of Φ
N
→Φ
P
is entirely symmetrical
to that of Φ
P
→Φ
N
. Figure 30.1.2, bottom shows the methodology for the ES flip and
waveforms of V
PP,
V
PN
, and I
L
during the flip operation, neglecting V
D
. In Φ
E
, the N
flip
equal
split causes V
PP
to decrease (1/N
flip
)×V
BAT
per step, discharging C
P
. Therefore, the I
L
rising
slope (S
R
) in Φ
E1
is decreased by (1/N
flip
)×(V
BAT
/L) per step from V
BAT
/L, and the I
L
falling
slope (S
F
) in Φ
E2
is increased by (1/N
flip
)×(V
BAT
/L) per step from (1/N
flip
)·(V
BAT
/L).
Conversely, in Φ
I
, V
PN
is increased by (1/N
flip
)×V
BAT
per step, and I
L
slopes are identical
to those of Φ
E
. The duty for each step becomes regular and symmetrical. Therefore, the
ES flip makes I
L_peak
lower and constant and equalizes the amounts of harvesting and
investing energy, thereby maximizing η
Flip
while preventing an excessive investment.
Figure 30.1.3 shows the overall structure of the N-step ES-SSHI with the multiple flip-
duty generator (MFDG). The input sensor monitors the V
PP
and V
PN
. When V
PT
< V
th
, all
controllers except for the input sensor are turned off for sleep mode. When V
PT
≥ V
th
, the
Harvest_start signal becomes high to enable the controllers for energy extraction. The
flip point (I
P
≈0) is sensed by a flip-point detector (FPD) that includes a current-starved
ring oscillator (CRSO) and a latched comparator. The Flip_start from the FPD sets Flip_EN
to enable three MFDGs in the flip operation only, which is hundreds of times shorter than
the non-flip operation, significantly reducing the power consumption. For a constant
I
L_peak
, the product of the n
th
rising slope of I
L
(S
R_n
) and the rising time of I
L
(D
R_n
) equals
the product of the n
th
falling slope of I
L
(S
F_n
) and the falling time of I
L
(D
F_n
). Therefore,
if the first D
R
is set to D
R_1
, all flip duties (D
R,
D
F
) are expressed as D
R_1
, and D
R
and D
F
are symmetric, as shown in Fig. 30.1.3, bottom. Based on this relation, the MFDG can
formulate multiple flip-duties via reconfigurable series capacitors. The capacitance of
C
D1
to C
D9
are all the same, and the number of C
D
connected in series is changed by the
capacitor selector. After the duty is set and M
D1
is turned off, I
bias
increases the gate
voltage of M
D5
(V
g_MD5
) with different slopes according to the C
D
sequencing. When V
g_MD5
reaches V
th
and turns M
D5
on, the drain voltage of M
D5
(V
D_MD5
) falls from the supply
voltage, causing the duty to be reset. Thanks to this multiple duty generation, only three
MFDGs can be used for every step, reducing the controller loss significantly. For
generating an accurate duty, the latency of the MFDG caused by parasitic components
should be negligible. Since the falling time of V
D_MD5
is minimized by using positive
feedback (PFB), a fast reset of duty is possible. Even though the multiple duties are
mathematically determined, an unexpected delay in D
F
can cause an inaccurate prediction
of zero I
L
point. For the stable flip operation without ZCD, the I
L
falling time, D
F
, is divided
into D
F,on
, where the switch is fully turned on, and D
F,diode
, which is operated by a diode
.
The D
F,on
(D
F,diode
) is the left-shifted (right-shifted) duty of calculated D
F
and shorter
(longer) than D
F
, which secures marginal time for zero current detection. M
5
and M
6
are
fully turned on when D
F,on
=1 and operate as a diode when D
F,on
=0 and D
F,diode
=1. The
switch/diode operation of M
5
and M
6
with optimized duties achieves both low conduction
loss and simple zero current detection in a passive way. Based on this operation, the
MFDGs generate D
R
, D
F,on
, and D
F,diode
N times. Then, Flip_N counter counts the number
of steps and finishes its flip operation.
The proposed N-step ES-SSHI was fabricated in the 0.18µm CMOS process and tested
with a MIDE PPA-1011 transducer. Figure 30.1.4 (top) shows the operating waveforms
and flip duties with 1H-to-10H inductors (f
PT
=130Hz, V
PT,OC
=2V, N
flip
=5). It proves that
10-step (N
flip
=5) ES flip works well with η
Flip
=91% (84%) when L=10µH (1µH). The three
MFDGs generate optimized D
R
, D
F,on
, and D
F,diode
allowing constant I
L_peak
of 95mA
(300mA). Figure30.1.4 (bottom) shows the measured periodic/shock operation and
simulated I
Q
waveform. Owing to the power gating of the MFDGs and FPD, I
Q
in sleep
mode is 22nA and the average of I
Q
during a periodic operation is 237nA. Figure 30.1.5
(top) demonstrates that this work achieves a power extraction improvement (FoM) of
×11.7 (×6.4) with a 10H (1H) inductor compared to the FBR. Figure 30.1.5 (middle)
shows that the power extraction is highest when N
flip
=7 (8) with 10H (1H). Also, this
work shows a high FoM with the smallest L. Figure 30.1.5 (bottom) shows the flip duties
and I
L
depending on N
flip
. Figure 30.1.6 presents a performance comparison table. A low
Q inductor of 1H-to-10H is used, achieving a FoM of 1170%. Moreover, 1H is the
lowest figure by 1/33 times compared to 33H, which is the lowest among previous
SSHI works. According to N
flip
, the capacitor sequencing of the MFDG changes the flip-
duties automatically, enabling a scalable 4-to-16 step with a peak η
Flip
of 91%. In addition,
the ES-SSHI shows a very low I
Q
of 22nA and it can harvest the energy from
periodic/shock excitations. Figure 30.1.7 shows a die micrograph and photos of the top
and bottom views of the PCB on which the die, L, and output capacitor, C, are mounted.
The chip occupies an area of 1.2mm
2
, and the total volume including the chip, L, and C
is 14.79mm
3
.
Acknowledgement:
This work was supported by the research project fund (1.220028.01) of UNIST (Ulsan
National Institute of Science and Technology). The chip fabrication and EDA tool were
supported by the IC design Education Center (IDEC), Korea.
References:
[1] Y.K. Ramadass and A.P. Chandrakasan, “An Efficient Piezoelectric Energy Harvesting
Interface Circuit Using a Bias-Flip Rectifier and Shared Inductor,” IEEE JSSC, vol. 45,
no.1, pp. 189–204, Jan. 2010.
[2] A. Morel et al., “Self-Tunable Phase-Shifted SECE Piezoelectric Energy-Harvesting IC
with a 30nW MPPT Achieving 446% Energy-Bandwidth Improvement and 94%
Efficiency,” ISSCC, pp. 488–489, Feb. 2020.
[3] Z. Chen et al., “A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-
Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3×
Energy-Extraction Improvement,” ISSCC, pp. 424–425, Feb. 2019.
978-1-6654-9016-0/23/$31.00 ©2023 IEEE
439
ISSCC 2023 / February 22, 2023 / 1:30 PM
DIGEST OF TECHNICAL PAPERS •
Figure 30.1.1: Proposed scalable N-step equal split SSHI (ES-SSHI) and previous
works.
Figure 30.1.2: Operation principle and waveforms of the proposed scalable N-step
ES-SSHI.
Figure 30.1.3: Overall structure of proposed N-step ES-SSHI with multiple flip-duty
generator (MFDG).
Figure 30.1.4: Measured operating waveforms of the proposed N-step ES-SSHI.
Figure 30.1.5: Measured harvested power of the proposed N-step ES-SSHI.
Figure 30.1.6: Performance summary and comparison with previous works.
30
• 2023 IEEE International Solid-State Circuits Conference
ISSCC 2023 PAPER CONTINUATIONS
978-1-6654-9016-0/23/$31.00 ©2023 IEEE
Figure 30.1.7: Die micrograph and photos of top and bottom of the PCB on which the
die, L and the output capacitor, C, are mounted.
Additional References:
[4] B. Ciftci et al., “A Low-Profile Autonomous Interface Circuit for Piezoelectric Micro-
Power Generators,” IEEE TCAS-I, vol. 68, no. 4, pp. 1458–1471, April 2021.
[5] S. Javvaji et al., “Analysis and Design of a Multi-Step Bias-Flip Rectifier for
Piezoelectric Energy Harvesting,” IEEE JSSC, vol. 54, no. 9, pp. 2590–2600, Sept. 2019.
[6] S. Li, et al., “A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output
Energy-Harvesting and Power-Management Platform with 1.2×10
5
Dynamic Range,
Integrated MPPT, and Multi-Modal Cold Start-Up,” ISSCC, pp. 656–657, Feb. 2022.
剩余31页未读,继续阅读
资源评论
LittleBrightness
- 粉丝: 0
- 资源: 132
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功