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DDR2-1066 JEDEC 标准,有助于学习 DDR2 控制时序,AC/DC 特性和 1066 Core Timing 参数,适用于市场上所有的 DDR2 产品。
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JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
JESD208
NOVEMBER 2007
JEDEC
STANDARD
SPECIALITY DDR2-1066 SDRAM
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and
approved by the JEDEC legal counsel.
JEDEC standards and publications are designed to serve the public interest through
eliminating misunderstandings between manufacturers and purchasers, facilitating
interchangeability and improvement of products, and assisting the purchaser in selecting
and obtaining with minimum delay the proper product for use by those other than JEDEC
members, whether the standard is to be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their
adoption may involve patents or articles, materials, or processes. By such action JEDEC
does not assume any liability to any patent owner, nor does it assume any obligation
whatever to parties adopting the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound
approach to product specification and application, principally from the solid state device
manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a
JEDEC standard or publication may be further processed and ultimately become an ANSI
standard.
No claims to be in conformance with this standard may be made unless all requirements
stated in the standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
publication should be addressed to JEDEC at the address below, or call (703) 907-7559
or www.jedec.org
Published by
©JEDEC Solid State Technology Association 2007
2500 Wilson Boulevard
Arlington, VA 22201-3834
This document may be downloaded free of charge; however JEDEC retains the
copyright on this material. By downloading this file the individual agrees not to
charge for or resell the resulting material.
PRICE: Please refer to the current
Catalog of JEDEC Engineering Standards and Publications online at
http://www.jedec.org/Catalog/catalog.cfm
Printed in the U.S.A.
All rights reserved
PLEASE!
DON’T VIOLATE
THE
LAW!
This document is copyrighted by JEDEC and may not be
reproduced without permission.
Organizations may obtain permission to reproduce a limited number of copies
through entering into a license agreement. For information, contact:
JEDEC Solid State Technology Association
2500 Wilson Boulevard
Arlington, Virginia 22201-3834
or call (703) 907-7559
JEDEC Standard No. 208
Page 1
SPECIALITY DDR2-1600 SDRAM
(From JEDEC Board Ballot JCB-07-64, JCB-07-69, and JCB-07-98, formulated under the cognizance of the JC-42.3 Subcommittee
on RAM Memories.)
Scope
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics,
packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC
compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. This specification was created based on
the DDR2 specification (JESD79-2) and some aspects of the DDR specification (JESD79). Each aspect of the changes for Specialty
DDR2-1066 SDRAM operation were considered and balloted. The accumulation of these ballots were then incorporated to prepare
this JESD208 specification, replacing whole sections and incorporating the changes into Functional Description and Operation.
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