JEDEC Standard No. 79-2C
Contents
1 Package ballout & addressing ......................................................................................................... 1
1.1 DDR2 SDRAM package ballout ...................................................................................................... 1
1.2 Quad-stacked/quad-die DDR2 SDRAM internal rank associations ................................................ 9
1.3 Input/output functional description ................................................................................................ 10
1.4 DDR2 SDRAM addressing ............................................................................................................ 11
2 Functional description ................................................................................................................... 12
2.1 Simplified state diagram ................................................................................................................ 12
2.2 Basic functionality ......................................................................................................................... 13
2.3 Power-up and initialization ............................................................................................................ 13
2.3.1 Power-up and initialization sequence ........................................................................................ 13
2.4 Programming the mode and extended mode registers ................................................................. 14
2.4.1 DDR2 SDRAM mode register (MR) ........................................................................................... 14
2.4.2 DDR2 SDRAM extended mode registers (EMR(#)) ................................................................... 15
2.4.3 Off-chip driver (OCD) impedance adjustment ............................................................................ 20
2.4.4 ODT (on-die termination) ........................................................................................................... 23
2.4.5 ODT related timings ................................................................................................................... 23
2.5 Bank activate command ................................................................................................................ 28
2.6 Read and write access modes ...................................................................................................... 28
2.6.1 Posted CAS ............................................................................................................................... 29
2.6.2 Burst mode operation ................................................................................................................ 30
2.6.3 Burst read command ................................................................................................................. 30
2.6.4 Burst write operation .................................................................................................................. 33
2.6.5 Write data mask ......................................................................................................................... 36
2.7 Precharge operation ..................................................................................................................... 37
2.7.1 Burst read operation followed by precharge .............................................................................. 38
2.7.2 Burst write followed by precharge .............................................................................................. 40
2.8 Auto precharge operation ............................................................................................................. 41
2.8.1 Burst read with auto precharge .................................................................................................. 42
2.8.2 Burst write with auto precharge ................................................................................................. 44
2.9 Refresh command ......................................................................................................................... 45
2.10 Self refresh operation .................................................................................................................... 46
2.11 Power-down .................................................................................................................................. 47
2.12 Asynchronous CKE LOW event .................................................................................................... 51
2.13 Input clock frequency change during precharge power down ....................................................... 52
2.14 SSC (Spread Spectrum Clocking) ................................................................................................ 53
2.14.1 Terms and definitions ................................................................................................................ 53
2.14.2 SSC (Spread Spectrum Clocking) Criteria ................................................................................. 53
2.14.3 Allowed SSC band .................................................................................................................... 53
2.15 No operation command ................................................................................................................. 53
2.16 Deselect command ....................................................................................................................... 53
3 Truth tables ..................................................................................................................................... 53
3.1 Command truth table .................................................................................................................... 53
3.2 Clock enable truth table. ............................................................................................................... 54
3.3 Data mask truth table. ................................................................................................................... 55
4 Absolute maximum DC ratings ...................................................................................................... 56
5 AC & DC operating conditions .................................................................................................
..... 56
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