MC33771 Base code

/************************************************************************************ * * Copyright (c) DU-POWER New Energy Technical Co., Ltd - All rights reserved * * file name: mc33771.c * * description: * mc33771. * * * revision history: * * Date Author Description * 2018/6/8 PSM initial version * *************************************************************************************/ #include "mc33771.h" #include "mc33664.h" #include "mc33771_app.h" #include "mc33771_config.h" #include "SpiIf.h" #include "common.h" #define DATA_LEN (5) #define DATA_RECV_LEN (DATA_LEN*CMU_CELL_NUMBERS+5) //max data length, 14cells #define MC33771_OV_UV_EN ( 0xFFEF ) //channel 5 is unused #define MC33771_ADC_CFG_DEFAULT_VALUE ( 0x043F ) #define MC33771_SYS_CFG1_DEFAULT_VALUE ( 0x9001 ) //sys_cfg1 default value #define MC33771_SYS_CFG_GLOBAL_GO2SLEEP ( 0x01 ) //go to sleep #define MC33771_SYS_CFG2_DEFAULT_VALUE ( 0x0330 ) #define MC33771_CBx_CFG_DEFAULT_VALUE ( 0x0000 ) #define MC33771_ADC2_OFFSET_COMP ( 0x4000 ) #define MC33771_SYS_DIAG_CT_OL_ODD ( 1U << 3 ) #define MC33771_SYS_DIAG_ISENSE_OL_DIAG ( 1U << 10) #define MC33771_SYS_DIAG_ANx_OL_DIAG ( 1U << 9 ) #define MC33771_SYS_DIAG_POLARITY ( 1U << 6 ) #define MC33771_SYS_CFG1_CB_MANUAL_PAUSE ( 1U << 5 ) #define MC33771_SYS_CFG2_NUMB_ODD ( 1U << 1 ) //even=0 odd=1 #define MC33771_ADC_CFG_PGA_GAIN ( 3 << 8 ) //011=3--256 #define MC33771_FAULT1_STATUS_IS_OL_FLT ( 5 ) #define MC33771_CB_EN ( 9 ) //bit 9 #define MC33771_SOFT_RST ( 1U << 4 ) #define MC33771_BUS_SW_ENABLE ( 1U << 4 ) #define MC33771_BUS_SW_DISABLE ( 0 << 4 ) #define MC33771_ADC_CFG_SOC ( 1U << 11) #define MC33771_ADC1_A_DEF ( 3 << 4 ) //3=0b11 16bit resolution #define MC33771_ADC1_B_DEF ( 3 << 2 ) //3=0b11 16bit resolution #define MC33771_CB_DRVEN ( 1U << 7 ) #define MC33771_CB_MANUAL_PAUSE ( 1U << 5 ) #define MC33771_CBx_EN ( 1U << 9 ) #define MC33771_I_MEAS_EN ( 1U << 9 ) #define MC33771_GO2DIAG ( 1U << 6 ) #define MIN_CELL_VOL_MV (983) //( 150 )150mv/0.15258=983 #define MAX_ERROR_COUNT ( 7 ) static uint8_t sendbuf[DATA_LEN] = {0}; //5 static uint8_t recvbuf[DATA_RECV_LEN] = {0}; //5*14 static void mc33771_append_crc8(uint8_t *, uint8_t); static uint8_t mc33771_check_crc8( uint8_t *, uint8_t); static void mc33771_dataframe(uint8_t *buffer, uint16_t data, uint8_t addr, uint8_t cid, command_t cmd); //crc table static const uint8_t crc_table[256] = { 0x00, 0x2f, 0x5e, 0x71, 0xbc, 0x93, 0xe2, 0xcd, 0x57, 0x78, 0x09, 0x26, 0xeb, 0xc4, 0xb5, 0x9a, 0xae, 0x81, 0xf0, 0xdf, 0x12, 0x3d, 0x4c, 0x63, 0xf9, 0xd6, 0xa7, 0x88, 0x45, 0x6a, 0x1b, 0x34, 0x73, 0x5c, 0x2d, 0x02, 0xcf, 0xe0, 0x91, 0xbe, 0x24, 0x0b, 0x7a, 0x55, 0x98, 0xb7, 0xc6, 0xe9, 0xdd, 0xf2, 0x83, 0xac, 0x61, 0x4e, 0x3f, 0x10, 0x8a, 0xa5, 0xd4, 0xfb, 0x36, 0x19, 0x68, 0x47, 0xe6, 0xc9, 0xb8, 0x97, 0x5a, 0x75, 0x04, 0x2b, 0xb1, 0x9e, 0xef, 0xc0, 0x0d, 0x22, 0x53, 0x7c, 0x48, 0x67, 0x16, 0x39, 0xf4, 0xdb, 0xaa, 0x85, 0x1f, 0x30, 0x41, 0x6e, 0xa3, 0x8c, 0xfd, 0xd2, 0x95, 0xba, 0xcb, 0xe4, 0x29, 0x06, 0x77, 0x58, 0xc2, 0xed, 0x9c, 0xb3, 0x7e, 0x51, 0x20, 0x0f, 0x3b, 0x14, 0x65, 0x4a, 0x87, 0xa8, 0xd9, 0xf6, 0x6c, 0x43, 0x32, 0x1d, 0xd0, 0xff, 0x8e, 0xa1, 0xe3, 0xcc, 0xbd, 0x92, 0x5f, 0x70, 0x01, 0x2e, 0xb4, 0x9b, 0xea, 0xc5, 0x08, 0x27, 0x56, 0x79, 0x4d, 0x62, 0x13, 0x3c, 0xf1, 0xde, 0xaf, 0x80, 0x1a, 0x35, 0x44, 0x6b, 0xa6, 0x89, 0xf8, 0xd7, 0x90, 0xbf, 0xce, 0xe1, 0x2c, 0x03, 0x72, 0x5d, 0xc7, 0xe8, 0x99, 0xb6, 0x7b, 0x54, 0x25, 0x0a, 0x3e, 0x11, 0x60, 0x4f, 0x82, 0xad, 0xdc, 0xf3, 0x69, 0x46, 0x37, 0x18, 0xd5, 0xfa, 0x8b, 0xa4, 0x05, 0x2a, 0x5b, 0x74, 0xb9, 0x96, 0xe7, 0xc8, 0x52, 0x7d, 0x0c, 0x23, 0xee, 0xc1, 0xb0, 0x9f, 0xab, 0x84, 0xf5, 0xda, 0x17, 0x38, 0x49, 0x66, 0xfc, 0xd3, 0xa2, 0x8d, 0x40, 0x6f, 0x1e, 0x31, 0x76, 0x59, 0x28, 0x07, 0xca, 0xe5, 0x94, 0xbb, 0x21, 0x0e, 0x7f, 0x50, 0x9d, 0xb2, 0xc3, 0xec, 0xd8, 0xf7, 0x86, 0xa9, 0x64, 0x4b, 0x3a, 0x15, 0x8f, 0xa0, 0xd1, 0xfe, 0x33, 0x1c, 0x6d, 0x42 }; static void mc33771_append_crc8(uint8_t *buffer, uint8_t len) { uint8_t tbl_idx; uint8_t crc; crc = 0x42; // seed while(len--) { tbl_idx = (crc ^ (*buffer)); crc = (crc_table[tbl_idx] ^ (crc << 8)) & 0xff; buffer++; } *buffer = crc & 0xFF; } static uint8_t mc33771_check_crc8(uint8_t *buffer, uint8_t len) { uint8_t tbl_idx; uint8_t crc; crc = 0x42; // seed while(len--) { tbl_idx = (crc ^ (*buffer)); crc = (crc_table[tbl_idx] ^ (crc << 8)) & 0xff; buffer++; } return crc; } void mc33771_init(void) { //TPL must use 33664 for translator mc33664_init(); //en pin init mc33664_enable(); //en pin set high __|-- } void mc33771_wakeup(void) { mc33664_wakeup(); } //5byte=40bit void mc33771_dataframe(uint8_t *buffer, uint16_t data, uint8_t addr, uint8_t cid, command_t cmd) { *(buffer +0) = (uint8_t)(data>>8 & 0xFF); //data h *(buffer +1) = (uint8_t)(data); //data l *(buffer +2) = (uint8_t)(addr); //addr *(buffer +3) = (uint8_t)( ((cid & 0xF)<<4) | (cmd & 0xF) ); //cid|cmd mc33771_append_crc8(buffer, 4); //crc } uint8_t mc33771_online_check(uint8_t index) { framedata_t fdata = {0, 0}; mc33771_readregister(index, INIT, 1, &fdata); if (fdata.addr != 0x81 ){ //Master/Slave=1 Memory Address=INIT=1 return 1; } return 0; } return_type mc33771_assign_cid(uint8_t cid, uint8_t sw_status) { return_type res; if(sw_status){ res = mc33771_writeregister(GLOBAL_CID, INIT, (cid | MC33771_BUS_SW_ENABLE), CmdWrLocal); //global id }else{ res = mc33771_writeregister(GLOBAL_CID, INIT, (cid | MC33771_BUS_SW_DISABLE), CmdWrLocal); //global id } return res; } return_type mc33771_busswitch(uint8_t cid, uint8_t status) { return_type res; if(status){ res = mc33771_writeregister(cid, INIT, (cid | MC33771_BUS_SW_ENABLE), CmdWrLocal); }else{ res = mc33771_writeregister(cid, INIT, (cid), CmdWrLocal); } return res; } return_type mc33771_enable_currentmeasure(uint8_t cid) { return_type res; framedata_t fdata = {0,0}; mc33771_readregister(cid, SYS_CFG1, 1, &fdata); //閸忓牐顕伴崘宥嗘暭閸愶拷 fdata.data |= MC33771_I_MEAS_EN; mc33771_writeregister(cid, SYS_CFG1, fdata.data, CmdWrLocal); res = mc33771_writeregister(cid, ADC_CFG, MC33771_ADC_CFG_DEFAULT_VALUE|MC33771_ADC_CFG_PGA_GAIN, CmdWrLocal); //mc33771_writeregister(cid, ADC_CFG, MC33771_ADC_CFG_DEFAULT_VALUE, CmdWrLocal); return res; } return_type mc33771_start_convertion(void) { return_type res; //0x043F 16bit 16bit res = mc33771_writeregister(GLOBAL_CID, ADC_CFG, (0x043F|MC33771_ADC_CFG_SOC|MC33771_ADC1_A_DEF|MC33771_ADC1_B_DEF), CmdWrGlobal); return res; } return_type mc33771_set_balance(uint8_t cid, uint8_t channel) { return_type res; framedata_t fdata = {0, 0}; channel = channel + CB1_CFG; //0x0C(CB1_CFG) -- 0x19(CB14_CFG) mc33771_readregister(cid, SYS_CFG1, 1, &fdata); fdata.data |= MC33771_CB_DRVEN; //all ch switch fdata.data &= ~(MC33771_CB_MANUAL_PAUSE);//individual ch switch mc33771_writeregister(cid, SYS_CFG1, fdata.data, CmdWrLocal); res = mc33771_writeregister(cid, channel, MC33771_CBx_EN|MC33771_CBx_CFG_DEFAULT_VALUE, CmdWrLocal); return res; } re