TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS439M
June 2007–Revised August 2012
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439M –JUNE 2007–REVISED AUGUST 2012
Contents
1 TMS320F2833x, TMS320F2823x DSCs .................................................................................. 10
1.1 Features .................................................................................................................... 10
1.2 Getting Started ............................................................................................................. 11
2 Introduction ...................................................................................................................... 12
2.1 Pin Assignments ........................................................................................................... 14
2.2 Signal Descriptions ........................................................................................................ 23
3 Functional Overview .......................................................................................................... 33
3.1 Memory Maps .............................................................................................................. 34
3.2 Brief Descriptions .......................................................................................................... 41
3.2.1 C28x CPU ....................................................................................................... 41
3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 41
3.2.3 Peripheral Bus .................................................................................................. 41
3.2.4 Real-Time JTAG and Analysis ................................................................................ 42
3.2.5 External Interface (XINTF) .................................................................................... 42
3.2.6 Flash ............................................................................................................. 42
3.2.7 M0, M1 SARAMs ............................................................................................... 42
3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 43
3.2.9 Boot ROM ........................................................................................................ 43
3.2.9.1 Peripheral Pins Used by the Bootloader ........................................................ 44
3.2.10 Security .......................................................................................................... 44
3.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 46
3.2.12 External Interrupts (XINT1–XINT7, XNMI) .................................................................. 46
3.2.13 Oscillator and PLL .............................................................................................. 46
3.2.14 Watchdog ........................................................................................................ 46
3.2.15 Peripheral Clocking ............................................................................................. 46
3.2.16 Low-Power Modes .............................................................................................. 46
3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 47
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 47
3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 47
3.2.20 Control Peripherals ............................................................................................. 48
3.2.21 Serial Port Peripherals ......................................................................................... 48
3.3 Register Map ............................................................................................................... 49
3.4 Device Emulation Registers .............................................................................................. 51
3.5 Interrupts .................................................................................................................... 52
3.5.1 External Interrupts .............................................................................................. 56
3.6 System Control ............................................................................................................ 57
3.6.1 OSC and PLL Block ............................................................................................ 58
3.6.1.1 External Reference Oscillator Clock Option .................................................... 59
3.6.1.2 PLL-Based Clock Module ......................................................................... 60
3.6.1.3 Loss of Input Clock ................................................................................ 61
3.6.2 Watchdog Block ................................................................................................. 62
3.7 Low-Power Modes Block ................................................................................................. 63
4 Peripherals ....................................................................................................................... 64
4.1 DMA Overview ............................................................................................................. 64
4.2 32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2 ..................................................................... 66
4.3 Enhanced PWM Modules ................................................................................................ 68
4.4 High-Resolution PWM (HRPWM) ....................................................................................... 72
4.5 Enhanced CAP Modules ................................................................................................. 73
4.6 Enhanced QEP Modules ................................................................................................. 75
4.7 Analog-to-Digital Converter (ADC) Module ............................................................................ 77
4.7.1 ADC Connections if the ADC Is Not Used .................................................................. 81
2 Contents Copyright © 2007–2012, Texas Instruments Incorporated
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439M –JUNE 2007–REVISED AUGUST 2012
4.7.2 ADC Registers .................................................................................................. 82
4.7.3 ADC Calibration ................................................................................................. 83
4.8 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 83
4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 86
4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) .......................................... 91
4.11 Serial Peripheral Interface (SPI) Module (SPI-A) ..................................................................... 95
4.12 Inter-Integrated Circuit (I2C) ............................................................................................. 98
4.13 GPIO MUX ................................................................................................................. 99
4.14 External Interface (XINTF) .............................................................................................. 106
5 Device Support ................................................................................................................ 108
5.1 Device and Development Support Tool Nomenclature ............................................................. 108
5.2 Documentation Support ................................................................................................. 110
5.3 Community Resources .................................................................................................. 115
6 Electrical Specifications ................................................................................................... 116
6.1 Absolute Maximum Ratings ............................................................................................ 116
6.2 Recommended Operating Conditions ................................................................................. 117
6.3 Electrical Characteristics ................................................................................................ 117
6.4 Current Consumption .................................................................................................... 118
6.4.1 Reducing Current Consumption ............................................................................. 120
6.4.2 Current Consumption Graphs ............................................................................... 121
6.4.3 Thermal Design Considerations ............................................................................. 122
6.5 Emulator Connection Without Signal Buffering for the DSP ....................................................... 123
6.6 Timing Parameter Symbology .......................................................................................... 124
6.6.1 General Notes on Timing Parameters ...................................................................... 124
6.6.2 Test Load Circuit .............................................................................................. 124
6.6.3 Device Clock Table ........................................................................................... 125
6.7 Clock Requirements and Characteristics ............................................................................. 126
6.8 Power Sequencing ....................................................................................................... 127
6.8.1 Power Management and Supervisory Circuit Solutions .................................................. 128
6.9 General-Purpose Input/Output (GPIO) ................................................................................ 131
6.9.1 GPIO - Output Timing ........................................................................................ 131
6.9.2 GPIO - Input Timing .......................................................................................... 132
6.9.3 Sampling Window Width for Input Signals ................................................................. 133
6.9.4 Low-Power Mode Wakeup Timing .......................................................................... 134
6.10 Enhanced Control Peripherals ......................................................................................... 139
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 139
6.10.2 Trip-Zone Input Timing ....................................................................................... 139
6.10.3 High-Resolution PWM Timing ............................................................................... 140
6.10.4 Enhanced Capture (eCAP) Timing ......................................................................... 140
6.10.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing ................................................... 141
6.10.6 ADC Start-of-Conversion Timing ............................................................................ 142
6.11 External Interrupt Timing ................................................................................................ 142
6.12 I2C Electrical Specification and Timing ............................................................................... 143
6.13 Serial Peripheral Interface (SPI) Timing .............................................................................. 143
6.13.1 Master Mode Timing .......................................................................................... 143
6.13.2 SPI Slave Mode Timing ...................................................................................... 148
6.14 External Interface (XINTF) Timing ..................................................................................... 151
6.14.1 USEREADY = 0 ............................................................................................... 151
6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) ............................................. 152
6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................ 153
6.14.4 XINTF Signal Alignment to XCLKOUT ..................................................................... 155
6.14.5 External Interface Read Timing ............................................................................. 156
6.14.6 External Interface Write Timing ............................................................................. 158
Copyright © 2007–2012, Texas Instruments Incorporated Contents 3
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012
www.ti.com
6.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................ 160
6.14.8 External Interface Ready-on-Write Timing With One External Wait State ............................. 163
6.14.9 XHOLD and XHOLDA Timing ............................................................................... 166
6.15 On-Chip Analog-to-Digital Converter .................................................................................. 169
6.15.1 ADC Power-Up Control Bit Timing .......................................................................... 170
6.15.2 Definitions ...................................................................................................... 171
6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................ 172
6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 173
6.15.5 Detailed Descriptions ......................................................................................... 174
6.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 175
6.16.1 McBSP Transmit and Receive Timing ...................................................................... 175
6.16.2 McBSP as SPI Master or Slave Timing .................................................................... 178
6.17 Flash Timing .............................................................................................................. 182
6.18 Migrating Between F2833x Devices and F2823x Devices ......................................................... 184
7 L-to-M Revision History .................................................................................................... 185
8 K-to-L Revision History .................................................................................................... 186
9 Thermal and Mechanical Data ............................................................................................ 187
4 Contents Copyright © 2007–2012, Texas Instruments Incorporated
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439M –JUNE 2007–REVISED AUGUST 2012
List of Figures
2-1 F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View) ...................................................................... 14
2-2 F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View) .............................. 16
2-3 F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Upper Right Quadrant) (Bottom View)............................. 17
2-4 F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Lower Left Quadrant) (Bottom View) .............................. 18
2-5 F2833x, F2823x 179-Ball ZHH MicroStar BGA ™(Lower Right Quadrant) (Bottom View)............................. 19
2-6 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Left Quadrant) (Bottom View)...................................... 20
2-7 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Right Quadrant) (Bottom View).................................... 21
2-8 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Left Quadrant) (Bottom View)...................................... 22
2-9 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Right Quadrant) (Bottom View).................................... 22
3-1 Functional Block Diagram ...................................................................................................... 34
3-2 F28335, F28235 Memory Map ................................................................................................. 36
3-3 F28334, F28234 Memory Map ................................................................................................. 37
3-4 F28332, F28232 Memory Map ................................................................................................. 37
3-5 External and PIE Interrupt Sources............................................................................................ 53
3-6 External Interrupts................................................................................................................ 53
3-7 Multiplexing of Interrupts Using the PIE Block ............................................................................... 54
3-8 Clock and Reset Domains ...................................................................................................... 57
3-9 OSC and PLL Block Diagram................................................................................................... 58
3-10 Using a 3.3-V External Oscillator............................................................................................... 59
3-11 Using a 1.9-V External Oscillator............................................................................................... 59
3-12 Using the Internal Oscillator .................................................................................................... 59
3-13 Watchdog Module ................................................................................................................ 62
4-1 DMA Functional Block Diagram ................................................................................................ 65
4-2 CPU-Timers....................................................................................................................... 66
4-3 CPU-Timer Interrupt Signals and Output Signal ............................................................................. 66
4-4 Time-Base Counter Synchronization Scheme 3 ............................................................................. 68
4-5 ePWM Submodules Showing Critical Internal Signal Interconnections ................................................... 71
4-6 eCAP Functional Block Diagram ............................................................................................... 73
4-7 eQEP Functional Block Diagram............................................................................................... 75
4-8 Block Diagram of the ADC Module ............................................................................................ 78
4-9 ADC Pin Connections With Internal Reference .............................................................................. 79
4-10 ADC Pin Connections With External Reference ............................................................................. 80
4-11 McBSP Module .................................................................................................................. 84
4-12 eCAN Block Diagram and Interface Circuit ................................................................................... 87
4-13 eCAN-A Memory Map ........................................................................................................... 88
4-14 eCAN-B Memory Map ........................................................................................................... 89
4-15 Serial Communications Interface (SCI) Module Block Diagram............................................................ 94
4-16 SPI Module Block Diagram (Slave Mode) .................................................................................... 97
4-17 I2C Peripheral Module Interfaces .............................................................................................. 98
4-18 GPIO MUX Block Diagram .................................................................................................... 100
4-19 Qualification Using Sampling Window ....................................................................................... 105
4-20 External Interface Block Diagram............................................................................................. 106
4-21 Typical 16-bit Data Bus XINTF Connections................................................................................ 107
4-22 Typical 32-bit Data Bus XINTF Connections................................................................................ 107
5-1 Example of F2833x, F2823x Device Nomenclature........................................................................ 109
6-1 Typical Operational Current Versus Frequency (F28335, F28235, F28334, F28234)................................. 122
6-2 Typical Operational Power Versus Frequency (F28335, F28235, F28334, F28234) .................................. 122
Copyright © 2007–2012, Texas Instruments Incorporated List of Figures 5
