#ifndef _W5300_H_
#define _W5300_H_
/**
* \file w5300.h
* Definition register of W5300 and basic I/O functions.
*
* This file defines the memory map and values of W5300 register.\n
* Also, it defines the basic I/O function to access register of W5300.
*
* \author MidnightCow
* \date 15/05/2008
* \version 1.1.0
*
* ---------- ------- ----------- ----------------------------
* Date Version Author Description
* ---------- ------- ----------- ----------------------------
* 24/03/2008 1.0.0 MidnigthCow Release with W5300 launching
* ---------- ------- ----------- ----------------------------
* 01/05/2008 1.0.1 MidnightCow Modify a logical error in iinchip_irq(). Refer to M_01052008
* ---------- ------- ----------- ----------------------------
* 15/05/2008 1.1.0 MidnightCow Refer to M_15052008
* Delete getSn_DPORTR() because \ref Sn_DPORTR is write-only.
* Replace 'Sn_DHAR2' with 'Sn_DIPR' in \ref getSn_DIPR().
* ---------- ------- ----------- ----------------------------
* 08/08/2008 1.2.0 MidnightCow Refer to M_08082008
* Add IINCHIP_CRITICAL_SECTION_ENTER() & IINCHIP_CRITICAL_SECTION_EXIT() to wiz_read_buf() and wiz_write_buf().
* Modify the description of \ref Sn_SSR and \ref close().</td>
* ---------- ------- ----------- ----------------------------
*/
#include "iinchip_conf.h"
#include "types.h"
/**
* Mode register.
*/
#define MR (__DEF_IINCHIP_MAP_BASE__)
#define MR0 MR
#define MR1 (MR + 1)
/**
* Indirect mode address register.
*/
#define IDM_AR (__DEF_IINCHIP_MAP_BASE__ + 0x02)
#define IDM_AR0 IDM_AR
#define IDM_AR1 (IDM_AR + 1)
/**
* Indirect mode data register.
*/
#define IDM_DR (__DEF_IINCHIP_MAP_BASE__ + 0x04)
#define IDM_DR0 (__DEF_IINCHIP_MAP_BASE__ + 0x04)
#define IDM_DR1 (IDM_DR + 1)
/**
* Interrupt register
*/
#define IR (COMMON_REG_BASE + 0x02)
#define IR0 IR
#define IR1 (IR + 1);
/**
* Interrupt mask register
*/
#define IMR (COMMON_REG_BASE + 0x04)
#define IMR0 IMR
#define IMR1 (IMR + 1)
//#define ICFGR (COMMON_REG_BASE + 0x06)
//#define ICFGR0 ICFGR
//#define ICFGR1 (ICFGR0 + 1)
/**
* Source hardware address register
*/
#define SHAR (COMMON_REG_BASE + 0x08)
#define SHAR0 SHAR
#define SHAR1 (SHAR + 1)
#define SHAR2 (SHAR + 2)
#define SHAR3 (SHAR + 3)
#define SHAR4 (SHAR + 4)
#define SHAR5 (SHAR + 5)
/**
* Gateway IP address register
*/
#define GAR (COMMON_REG_BASE + 0x10)
#define GAR0 GAR
#define GAR1 (GAR + 1)
#define GAR2 (GAR + 2)
#define GAR3 (GAR + 3)
/**
* Subnet mask register
*/
#define SUBR (COMMON_REG_BASE + 0x14)
#define SUBR0 SUBR
#define SUBR1 (SUBR + 1)
#define SUBR2 (SUBR + 2)
#define SUBR3 (SUBR + 3)
/**
* Source IP address register
*/
#define SIPR (COMMON_REG_BASE + 0x18)
#define SIPR0 SIPR
#define SIPR1 (SIPR + 1)
#define SIPR2 (SIPR + 2)
#define SIPR3 (SIPR + 3)
/**
* Retransmittion timeout-period register
*/
#define RTR (COMMON_REG_BASE + 0x1C)
#define RTR0 RTR
#define RTR1 (RTR + 1)
/**
* Retransmittion retry count reigster
*/
#define RCR (COMMON_REG_BASE + 0x1E)
#define RCR0 RCR
#define RCR1 (RCR + 1)
/**
* Transmit memory size of each SOCKET reigster
*/
#define TMS01R (COMMON_REG_BASE + 0x20)
#define TMS23R (TMS01R + 2) /**< Refer to TMS01R. */
#define TMS45R (TMS01R + 4) /**< Refer to TMS01R. */
#define TMS67R (TMS01R + 6) /**< Refer to TMS01R. */
#define TMSR0 TMS01R
#define TMSR1 (TMSR0 + 1)
#define TMSR2 (TMSR0 + 2)
#define TMSR3 (TMSR0 + 3)
#define TMSR4 (TMSR0 + 4)
#define TMSR5 (TMSR0 + 5)
#define TMSR6 (TMSR0 + 6)
#define TMSR7 (TMSR0 + 7)
/**
* Transmit memory size of each SOCKET reigster
*/
#define RMS01R (COMMON_REG_BASE + 0x28)
#define RMS23R (RMS01R + 2) /**< Refer to RMS01R. */
#define RMS45R (RMS01R + 4) /**< Refer to RMS01R. */
#define RMS67R (RMS01R + 6) /**< Refer to RMS01R. */
#define RMSR0 RMS01R
#define RMSR1 (RMSR0 + 1)
#define RMSR2 (RMSR0 + 2)
#define RMSR3 (RMSR0 + 3)
#define RMSR4 (RMSR0 + 4)
#define RMSR5 (RMSR0 + 5)
#define RMSR6 (RMSR0 + 6)
#define RMSR7 (RMSR0 + 7)
/**
* Memory type register
*/
#define MTYPER (COMMON_REG_BASE + 0x30)
#define MTYPER0 MTYPER
#define MTYPER1 (MTYPER + 1)
/**
* Authentication type register
*/
#define PATR (COMMON_REG_BASE + 0x32)
#define PATR0 PATR
#define PATR1 (PATR + 1)
//#define PPPALGOR (COMMON_REG_BASE + 0x34)
//#define PPPALGOR0 PPPALGOR
//#define PPPALGOR1 (PPPALGOR + 1)
/**
* PPP link control protocol request timer register
*/
#define PTIMER (COMMON_REG_BASE + 0x36)
#define PTIMER0 PTIMER
#define PTIMER1 (PTIMER + 1)
/**
* PPP LCP magic number register
*/
#define PMAGICR (COMMON_REG_BASE + 0x38)
#define PMAGICR0 PMAGICR
#define PMAGICR1 (PMAGICR + 1)
//#define PSTATER (COMMON_REG_BASE + 0x3A)
//#define PSTATER0 PSTATER
//#define PSTATER1 (PSTATER + 1)
/**
* PPPoE session ID register
*/
#define PSIDR (COMMON_REG_BASE + 0x3C)
#define PSIDR0 PSIDR
#define PSIDR1 (PSIDR + 1)
/**
* PPPoE destination hardware address register
*/
#define PDHAR (COMMON_REG_BASE + 0x40)
#define PDHAR0 PDHAR
#define PDHAR1 (PDHAR + 1)
#define PDHAR2 (PDHAR + 2)
#define PDHAR3 (PDHAR + 3)
#define PDHAR4 (PDHAR + 4)
#define PDHAR5 (PDHAR + 5)
/**
* Unreachable IP address register
*
* RESET : 0.0.0.0 \n
* When trying to transmit UDP data to destination port number which is not open,
* W5300 can receive ICMP (Destination port unreachable) packet. \n
* In this case, IR(IR_DPUR) becomes '1'.
* And destination IP address and unreachable port number of ICMP packet
* can be acquired through UIPR and UPORTR.
*/
#define UIPR (COMMON_REG_BASE + 0x48)
#define UIPR0 UIPR
#define UIPR1 (UIPR + 1)
#define UIPR2 (UIPR + 2)
#define UIPR3 (UIPR + 3)
/**
* Unreachable port number register
*/
#define UPORTR (COMMON_REG_BASE + 0x4C)
#define UPORTR0 UPORTR
#define UPORTR1 (UPORT + 1)
/**
* Fragment MTU register
*/
#define FMTUR (COMMON_REG_BASE + 0x4E)
#define FMTUR0 FMTUR
#define FMTUR1 (FMTUR + 1)
//#define Sn_RTCR(n) (COMMON_REG_BASE + 0x50 + n*2)
//#define Sn_RTCR0(n) Sn_RTCR(n)
//#define Sn_RTCR1(n) (Sn_RTCR(n)+1)
/**
* PIN 'BRDYn' configure register
*/
#define Pn_BRDYR(n) (COMMON_REG_BASE + 0x60 + n*4)
#define Pn_BRDYR0(n) Pn_BRDYR(n)
#define Pn_BRDYR1(n) (Pn_BRDYR(n) + 1)
/**
* PIN 'BRDYn' buffer depth Register
*/
#define Pn_BDPTHR(n) (COMMON_REG_BASE + 0x60 + n*4 + 2)
#define Pn_BDPTHR0(n) Pn_BDPTHR(n)
#define Pn_BDPTHR1(n) (Pn_BDPTHR(n) + 1)
/**
* W5300 identification register
*/
#define IDR (COM
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W5300_Drv.rar (44个子文件)
W5300_Drv
W5300_Drv.sln 884B
include
md5.h 584B
stdarg.h 2KB
socket.h 2KB
types.h 2KB
xscale.h 6KB
iinchip_conf.h 2KB
w5300.h 28KB
main.h 1KB
lstring.h 994B
serial.h 1KB
time.h 640B
W5300_Drv.vcxproj 5KB
W5300_Drv.vcxproj.user 143B
W5300_Drv.sdf 1.71MB
ipch
w5300_drv-fb714ad7
Debug
vc100.idb 59KB
W5300_Drv.lastbuildstate 48B
CL.write.1.tlog 4KB
CL.read.1.tlog 9KB
rc.write.1.tlog 310B
rc.read.1.tlog 302B
W5300_Drv_manifest.rc 208B
socket.obj 12KB
cl.command.1.tlog 8KB
link-cvtres.read.1.tlog 2B
W5300_Drv.pdb 19KB
lstring.obj 17KB
main.obj 11KB
link.write.1.tlog 2B
W5300_Drv.unsuccessfulbuild 0B
link-cvtres.write.1.tlog 2B
w5300.obj 33KB
link.command.1.tlog 2B
rc.command.1.tlog 552B
link.read.1.tlog 2B
W5300_Drv.exe.embed.manifest.res 68B
W5300_Drv.exe.embed.manifest 2B
W5300_Drv.exe.intermediate.manifest 381B
md5.obj 12KB
serial.obj 3KB
W5300_Drv.log 2KB
vc100.pdb 60KB
W5300_Drv.vcxproj.filters 3KB
W5300_Drv.suo 23KB
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