UART.ZIP_lattice_uart_uart用vhdl来

Universal Asynchronous

Receiver/Transmitter

April 2011 Reference Design 1011

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to-serial conversion on the 8-bit data received from the CPU. In order to synchronize the asynchronous serial data

and to insure the data integrity, start, parity and stop bits are added to the serial data. An example of the UART

frame format is shown in Figure 2.

Figure 1. UART Block Diagram

Figure 2. UART Frame Format: (1 Start Bit, 8 Data Bits, 1 Parity Bit, 1 Stop Bit)

2

• Raster performance than industry standard hardwired devices

• Standard CPU Interface

• Separate interrupt lines for data received (RxRdyn) and data transmitted (TxRdyn)

• A common interrupt line for all internal UART data and error events. Interrupt conditions include: receiver line

• Fully-prioritized interrupt system control

• MODEM interface functions (CTS, RTS, DSR, DTR, RI and DCD)

• Fully programmable serial interface characteristics:

3

The UART contains two data buffering registers (RBR and THR), three status registers (IIR, LSR, and MSR), and

three control registers (IER, LCR, and MCR). These registers and their addresses are shown below. Further infor-

mation on the data buffering registers can be found in the Transmitter and Receiver sections of this document. Note

ADSn Input Address strobe

CS Input Chip select

RDn Input Read

WRn Input Write

DDIS Output Driver disable

4

Four prioritized interrupt levels and sources:

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