UART.zip_6678串口_barieu_c6678 uart_c6678中UART_uart dsp6678

/* * C:\Texas Instruments\mcsdk_2_00_05_17\tools\boot_loader\ibl\src\hw\uart\c66x_uart * C:\Texas Instruments\pdk_C6678_1_0_0_17\packages\ti\platform\evmc6678l\platform_lib\include */ #include <stdio.h> #include <ti\csl\csl_bootcfgAux.h> #include <ti\csl\csl_pscAux.h> #include "common.h" #define UART_BASE_ADDR 0x02540000 //#define BAUD_9600 1085 CSL_BootcfgRegs * boot_cfg_regs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS; CSL_PllcRegs * pllc_regs = (CSL_PllcRegs * )0x02310000; CSL_UartRegs* uart_registers = (CSL_UartRegs*)(UART_BASE_ADDR); void KeyStone_main_PLL_init ( unsigned int main_PLLM, unsigned int main_PLLD) { /* *CLK_in = 100 MHz * main CLK = CLK_in * (PLL_M + 1) / ( SECCTL[22:19] *(PLL_D + 1) ) * = 100 * (19 + 1) / ( 2 * (0 + 1)) * = 1000 MHz = 1 GHz */ unsigned int i; if(0<main_PLLM&&main_PLLM<=4096&&0<main_PLLD&&main_PLLD<=64) { CSL_BootCfgUnlockKicker(); boot_cfg_regs->CORE_PLL_CTL1 |= 0x00000040; //Set ENSAT = 1 printf("Initialize main PLL = x%d/%d\n", main_PLLM, main_PLLD); //Bypass the PLL, PLL OUTPUT_DIVIDER = 2 pllc_regs->SECCTL |= 0x00880000; /*Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect*/ pllc_regs->PLLCTL= pllc_regs->PLLCTL&(~(1<<5)); /*Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode)*/ pllc_regs->PLLCTL= pllc_regs->PLLCTL&(~(1<<0)); /*Wait for 4 input clock cycles to ensure PLLC switches to bypass mode properly*/ for(i=0; i< 4*8192/5+1; i++) asm(" nop 5"); /*The PLL has a bandgap generator circuit driving the PLL voltage regulator. In order to ensure proper PLL startup, the PLL power_down pin needs to be toggled. This is accomplished by toggling the ¡°PLLPWRDN¡± bit in the PLLCTL register. This needs to be done before the main PLL initialization sequence. */ pllc_regs->PLLCTL |= (1<<1); //Power down the PLL // wait for 5 us (min) for(i=0; i< 1000; i++) asm(" nop 5"); // Verify if pll is in power down if ((pllc_regs->PLLCTL & (1<<1)) !=0 ) { pllc_regs->PLLCTL &= ~(1<<1); // Power up PLL // Wait PLL Stabilization time that is 150 usec for(i=0; i< 30000; i++) asm(" nop 5"); } /*In PLLCTL, write PLLRST = 1 (PLL is reset)*/ pllc_regs->PLLCTL= pllc_regs->PLLCTL|(1<<3); /*Program the required multiplier and divider values*/ //pllc_regs->PREDIV= 0x8000; /*PLLM[5:0] bits of the multiplier is controlled by the PLLM register inside the PLL controller and PLLM[12:6] bits are controlled by the chip level register. MAINPLLCTL0 register PLLM[12:6] bits should be written just before writing to PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller.*/ boot_cfg_regs->CORE_PLL_CTL0 = ((main_PLLM-1)<<24)| /*BWADJ[7:0]*/ (((main_PLLM*2-1)&0x1FC0)<<6)|(main_PLLD-1); pllc_regs->PLLM= (main_PLLM*2-1)&0x3F; boot_cfg_regs->CORE_PLL_CTL1 = 0x00000040 /*Set ENSAT bit = 1*/ |(main_PLLM-1)>>8; /*BWADJ[11:8]*/ //pllc_regs->POSTDIV= 0x8000; pllc_regs->PLLDIV8 = 4;//200M /*Wait 1000 ns for PLL reset*/ for(i=0; i< 1500/5+1; i++) asm(" nop 5"); /*In PLLCTL, write PLLRST = 0 to bring PLL out of reset*/ pllc_regs->PLLCTL= pllc_regs->PLLCTL&(~(1<<3)); /*Wait 2000 input clock cycles for PLL to lock*/ for(i=0; i< 2000*8192/5+1; i++) asm(" nop 5"); //clear the bypass bit, enable PLL pllc_regs->SECCTL &= ~(0x00800000); /*Set the PLLEN bit in PLLCTL to 1 to enable PLL mode*/ pllc_regs->PLLCTL= pllc_regs->PLLCTL|(1<<0); } } //Input clk = 1G/6 = 166.667M void uart_init(unsigned int baudrate) { uint8_t DLL_val = 0; uint8_t DLH_val = 0; unsigned int baudrate_cfg = 1000000000/(96*baudrate);// 1G/(6*16*Buadrate) /* Setting baud rate to 9600 */ DLL_val = (uint8_t )(0x00FF & baudrate_cfg); DLH_val = (uint8_t )(0x00FF & (baudrate_cfg >> 8)); /* Allows access to the divisor latches of the baud generator during a read or write operation (DLL and DLH) */ uart_registers->LCR = 0x80; /* Set the baudrate,for accessing LCR[7] should be enable */ uart_registers->DLL = DLL_val; uart_registers->DLH = DLH_val; /* Allows access to the receiver buffer register (RBR), the transmitter holding register (THR), and the interrupt enable register (IER) selected. */ uart_registers->LCR = 0x18; /* Disable THR, RHR, Receiver line status interrupts */ uart_registers->IER = 0; /* If autoflow control is desired, * write appropriate values to the modem * control register (MCR). Note that all UARTs * do not support autoflow control, see * the device-specific data manual for supported features. * * MCR * ==================================================== * Bit Field Value Description * 5 AFE 0 Autoflow control is disabled * 4 LOOP 0 Loop back mode is disabled. * 1 RTS 0 RTS control (UARTn_RTS is disabled, * UARTn_CTS is only enabled.) * ===================================================== * * */ uart_registers->MCR = 0; uart_registers->MDR = 0;//16¡Á oversampling /* Choose the desired response to * emulation suspend events by configuring * the FREE bit and enable the UART by setting * the UTRST and URRST bits in the power and * emulation management register (PWREMU_MGMT). * * * PWREMU_MGMT * ================================================= * Bit Field Value Description * 14 UTRST 1 Transmitter is enabled * 13 URRST 1 Receiver is enabled * 0 FREE 1 Free-running mode is enabled * =================================================== * */ uart_registers->PWREMU_MGMT = 0x6001; /* Cleanup previous data (rx trigger is also set to 0)*/ uart_registers->FCR = 0xC1; /* Setting the baud rate */ uart_registers->LCR = 0x80; /* Set the baudrate,for accessing LCR[7] should be enable */ uart_registers->DLL = DLL_val; uart_registers->DLH = DLH_val; uart_registers->LCR = 0x03; return; } void delay(unsigned int kk) { unsigned int i; for(i=0;i<kk;i++) { asm ("nop"); } } void UartWriteData(uint8_t uchByte) { while (!(CSL_FEXT(uart_registers->LSR, UART_LSR_THRE))) { delay(10000); } CSL_FINS(uart_registers->THR, UART_THR_DATA, uchByte); return; } Bool UartIsDataReady(void) { Bool DR_val = FALSE; if (CSL_UART_LSR_DR_READY == (CSL_FEXT(uart_registers->LSR, UART_LSR_DR))) { DR_val = TRUE; } return (DR_val); } uint8_t UartReadData(void) { uint8_t uRcvChar = 0; uRcvChar = CSL_FEXT(uart_registers->RBR, UART_RBR_DATA); return uRcvChar; } void uart_write_string(char * str, uint32_t length) { uint32_t i; if (length==0) { /*Maximum length is 80 */ length=80; } for(i = 0; i < length; i++) { if(str[i]=='\0') break; UartWriteData((uint8_t)str[i]); } UartWriteData((uint8_t)0x0D); UartWriteData((uint8_t)0x0A); } void uart_write_bytes(uint8_t * bytes_addr, unsigned int bytes_count) { unsigned int i; for(i = 0; i < bytes_count; i++) { UartWriteData(bytes_addr[i]); } }