Introduction
This tutorial is intended to familiarize you with the logic synthesis tool
called Design Compiler (DC) from Synopsys. It is not absolutely necessary
that you understand Verilog, but it is helpful that you know some very
basic verilog. Verilog is a hardware description language (HDL) that
describes the behavior of hardware in a "programming" language. Instead
of functions or procedures, verilog has modules. A module has an interface
of input, output, or bidirectional signals as shown here:
module MyModule (A, B, Z);
input A;
input [7:0] B;
output Z;
// other stuff
endmodule
The bus order [7:0] is order sensitive and is different than [0:7] if you
assign two buses. The simplest rule is to be consistent.
Modules may be instantiated like this:
MyModule instance0(.A(topA),.B(topB),.Z(topZ));
The ".A()" specifies that the signal at the top level (topA) is connected
to input A. This allows the signals to be written in any arbitrary order
such as:
MyModule instance0(.A(topA),.Z(topZ),.B(topB));
If it is excluded, you must preserve the order like this:
MyModule instance0(topA,topB,topZ);
That should be enough verilog to get you by for this tutorial. It is usually
the responsibility of the verilog designer to synthesis their own module.
This is because it is possible that synthesis can make bad inferences about
some verilog syntax. If you write good verilog (to be covered in class
briefly), you won't have to worry so much about this.
Synopsys Information
