szz.rar_verilog 数字钟_verilog数字钟_可调数码管_数字钟 verilog_数字钟verilog

module szz(clk1,clk2,en,changemin,changehou,cutmin,cuthou,saomiao,show_num,f); input clk1; input clk2; input en; input changemin; input changehou; input cutmin; input cuthou; output [3:1] saomiao; output show_num; output f; reg f; reg [3:1] saomiao; reg [7:1] show_num; reg [6:1] Sec,Min,Hou; reg [4:1] Time; reg [4:1] S1,S2,M1,M2,H1,H2; always@(posedge clk1) begin if(en == 1) begin Sec<=Sec+1; if(Sec == 59) begin Sec<=0; Min<=Min+1; end if(Min == 59&&Sec==59) begin Min<=0; Hou<=Hou+1; end if(Hou == 23&&Min == 59&&Sec == 59) Hou<=0; end else begin if(changemin==1) begin Min<=Min+1; if(Min==59) Min<=0; end else Min<=Min; if(changehou==1) begin Hou<=Hou+1; if(Hou==23) Hou<=0; end else Hou<=Hou; begin if(cutmin==1) begin Min<=Min-1; if(Min==0) Min<=59; end if(cuthou==1) begin Hou<=Hou-1; if(Hou==0) Hou<=23; end end end end always@(Min,Hou,Sec) begin if(Hou==8&&Min==0&&Sec==0||Hou==8&&Min==0&&Sec==1||Hou==8&&Min==0&&Sec==2||Hou==8&&Min==0&&Sec==3||Hou==8&&Min==0&&Sec==4) f=1; else f=0; end always@(Sec,Min,Hou) begin S2<=Sec/10; S1<=Sec%10; M2<=Min/10; M1<=Min%10; H2<=Hou/10; H1<=Hou%10; end always@(posedge clk2) begin if(saomiao==5) saomiao<=0; else saomiao<=saomiao+1; end always@(saomiao) begin case(saomiao) 3'b000:Time<=S1; 3'b001:Time<=S2; 3'b010:Time<=M1; 3'b011:Time<=M2; 3'b100:Time<=H1; 3'b101:Time<=H2; endcase end always@(Time) begin case(Time) 4'd0:show_num=7'b1111110; 4'd1:show_num=7'b0110000; 4'd2:show_num=7'b1101101; 4'd3:show_num=7'b1111001; 4'd4:show_num=7'b0110011; 4'd5:show_num=7'b1011011; 4'd6:show_num=7'b1011111; 4'd7:show_num=7'b1110000; 4'd8:show_num=7'b1111111; 4'd9:show_num=7'b1111011; endcase end endmodule