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###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 4.0
## \ \ Application : MIG
## / / Filename : readme.txt
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
## \ \ / \ Date Created : Tue Sept 21 2010
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Steps to run simulations using Modelsim/QuestaSim,
## Cadence IES, and Synopsys VCS
## Assumptions : Simulations are run in \sim folder of MIG output "Open IP
## Example Design" directory
## Reference :
## Revision History:
###############################################################################
MIG outputs script files required to run the simulations for Modelsim/QuestaSim,
Vivado Simulator, IES and VCS. These scripts are valid only for running
simulations for "Open IP Example Design"
1. How to run simulations in Modelsim/QuestaSim simulator
A) sim.do File :
a) The 'sim.do' file has commands to compile and simulate memory
interface design and run the simulation for specified period of time.
b) It has the syntax to Map the required libraries (unisims_ver,
unisim and secureip). The libraries should be mapped using
the following command
vmap unisims_ver <unisims_ver lib path>
vmap unisim <unisim lib path>
vmap secureip <secureip lib path>
Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file
c) Displays the waveforms that are listed with "add wave" command.
B) Steps to run the Modelsim/QuestaSim simulation:
a) The user should invoke the Modelsim/QuestaSim simulator GUI.
b) Change the present working directory path to the sim folder.
In Transcript window, at Modelsim/QuestaSim prompt, type the following
command to change directory path.
cd <sim directory path>
c) Run the simulation using sim.do file.
At Modelsim/QuestaSim prompt, type the following command:
do sim.do
d) To exit simulation, type the following command at Modelsim/QuestaSim
prompt:
quit -f
e) Verify the transcript file for the memory transactions.
2. How to run simulations in Vivado simulator
A) Following files are provided :
a) The 'xsim_run.bat' is the executable file for Vivado simulator under
MicroSoft Windows environment.
b) The 'xsim_run.sh' is the executable file for Vivado simulator under
Linux environment.
c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and
simulate memory interface design and run the simulation for specified
period of time.
d) xsim_options.tcl file has commands to add waveforms and simulation
period.
e) xsim_files.prj file has list of rtl files for simulating the design.
f) $XILINX_VIVADO environment variable must be set in order to compile
glbl.v file
B) Steps to run the Vivado Simulator simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using xsim_run.sh file under Linux environment and
xsim_run.bat under MicroSoft Windows environment.
c) Verify the transcript file for the memory transactions.
3. How to run Cadence IES Simulations
A) ies_run.sh File :
a) The "ies_run.sh" file contains the commands for simulation of the
hdl files.
b) Libraries must be mapped before running simulations. Following
procedure must be followed to before running simulations
1. Create two files named cds.lib and hdl.var in this directory
2. Create a directory 'worklib' in same directory.
mkdir worklib
3. Add following lines in the cds.lib file to map Xilinx libraries
DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim
DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver
DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip
DEFINE worklib ./worklib
4. ATTENTION: In above lines replace the path for libraries as per your
compiled Xilinx libraries directory
5. ATTENTION: Add the lines in the same order given above
6. Please make sure you need to map all Xilinx libraries mentioned above
7. Save and close the cds.lib file
Also, $XILINX_VIVADO environment variable must be set in order to
compile glbl.v file and the above mentioned library files
B) Steps to run the IES simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using ies_run.sh file. Type the following command:
./ies_run.sh
c) Verify the ies_sim.log file for the memory transactions.
4. How to run Synopsys VCS Simulations
A) vcs_run.sh File :
a) The "vcs_run.sh" file contains the commands for simulation of hdl files.
b) Libraries must be mapped before running simulations. Following
procedu
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09_ddr3_test.zip_MIG ddr3_ddr3 mig_frozenpgp_mig vivado_vivado (545个子文件)
xsim_run.bat 3KB
runme.bat 268B
runme.bat 268B
runme.bat 268B
runme.bat 229B
hw_ila_data_1_15612_1541511982.btree 0B
ddr3.dcp 2.17MB
ddr3.dcp 2.17MB
ila_0.dcp 1.32MB
ila_0.dcp 1.32MB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
compile.do 8KB
compile.do 8KB
compile.do 8KB
compile.do 8KB
sim.do 6KB
compile.do 886B
compile.do 862B
compile.do 821B
compile.do 811B
compile.do 805B
compile.do 781B
compile.do 740B
compile.do 730B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 303B
simulate.do 301B
simulate.do 294B
simulate.do 294B
simulate.do 291B
simulate.do 291B
simulate.do 195B
simulate.do 187B
simulate.do 185B
elaborate.do 183B
elaborate.do 175B
elaborate.do 173B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
run.f 8KB
run.f 522B
run.f 441B
hw_ila_data_1.ila 78KB
xil_txt.in 1KB
xsim.ini 19KB
xsim.ini 19KB
xsim.ini 19KB
vivado.jou 3KB
vivado.jou 857B
vivado.jou 833B
vivado.jou 758B
vivado.jou 730B
vivado.jou 722B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 521KB
runme.log 151KB
tcl.log 121KB
runme.log 21KB
runme.log 9KB
vivado.log 7KB
vivado.log 857B
ddr3_test.lpr 343B
.lpr 290B
elab.opt 188B
elab.opt 180B
elab.opt 178B
fsm_encoding.os 2KB
xil_txt.out 129B
vivado.pb 847KB
vivado.pb 241KB
vivado.pb 34KB
vivado.pb 13KB
ddr3_utilization_synth.pb 276B
ila_0_utilization_synth.pb 276B
clk_wiz_0_utilization_synth.pb 276B
xsim_files.prj 11KB
mig_a.prj 9KB
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